On Mon, Oct 2, 2017 at 6:06 PM, Chee, Tien Fong tien.fong.chee@intel.com wrote:
On Isn, 2017-10-02 at 12:04 +0200, Marek Vasut wrote:
On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:
On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote: > > > > From: Tien Fong Chee tien.fong.chee@intel.com > > Add function for both multiple DRAM bank and single DRAM > bank > size > initialization. This common functionality could be used by > every > single > SOCFPGA board. > > Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com I'd like TB on Gen5.
What is TB?
Tested-by Tested-by: Tien Fong Chee tien.fong.chee@intel.com
You want me resend the patch with Tested-by?
Uh no, that's not how TB works. You should get TB on your patches from someone else , not yourself .
oo...okay, i will ask ley foon help to verify.
Tested-by: Ley Foon Tan ley.foon.tan@intel.com