Otherwise NAND booting is likely to fail. Since this disables the NAND related clocks and SPL can't load the main U-Boot from NAND.
This problem was introduced with this patch:
e25fbe3f (gw_ventana: Move the DCD settings to spl code)
Signed-off-by: Stefan Roese sr@denx.de Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Tim Harvey tharvey@gateworks.com Cc: Stefano Babic sbabic@denx.de --- board/gateworks/gw_ventana/gw_ventana_spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index d6a5847..9712812 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -401,7 +401,7 @@ static void ccgr_init(void) writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); }