DDR3 support is tested and working with beaglebone hardware. Include a check for this board type and configure DDR3. The timings and other configuration match EVM SK.
Signed-off-by: Joel A Fernandes joelagnel@ti.com --- arch/arm/cpu/armv7/am33xx/board.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index ecc2671..13615cd 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -64,6 +64,11 @@ static inline int board_is_bone(void) return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); }
+static inline int board_is_bone_lt(void) +{ + return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); +} + static inline int board_is_evm_sk(void) { return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); @@ -124,7 +129,7 @@ static int read_eeprom(void) static short inline board_memory_type(void) { /* The following boards are known to use DDR3. */ - if (board_is_evm_sk()) + if (board_is_evm_sk() || board_is_bone_lt()) return EMIF_REG_SDRAM_TYPE_DDR3;
return EMIF_REG_SDRAM_TYPE_DDR2; @@ -283,7 +288,7 @@ int board_eth_init(bd_t *bis) return -1; }
- if (board_is_bone()) { + if (board_is_bone() || board_is_bone_lt()) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;