Hi Sughosh,
On Wed, 10 Jul 2013 23:04:45 +0530, Sughosh Ganu urwithsughosh@gmail.com wrote:
hi Albert,
On Wed Jul 10, 2013 at 02:30:30PM +0200, Albert ARIBAUD wrote:
You are correct re the other policies of the DDI0198E (ARM926EJ-S TRM) MMU -- page 3-11, bits 3-2 of the section descriptor. Note however that you may have to refer to your specific SoC's TRM or equivalent, as the SoC designer may have defined its own system-level cache and MMU architecture.
Note in any case that none of the policies mentioned in DDI0198E is described as read-allocate (let alone "read-allocate only" where writes would bypass the enabled cache); on the contrary, the only cache policies mentioned are write-through and write-back, both of which contradict cache bypass on write.
I was referring to the cache allocation policy mentioned in section 4.1 in the DDI0198E document -- this is also mentioned in table 12.1 in chapter 12 of the arm developers guide.
Can you please quote the exact part of 4.1 which describes the cache policy and then explain what you think it means exactly?
I was referring to this particular point in section 4.1 "Allocate on read-miss is supported. The caches perform critical-word first cache refilling."
This is not equivalent to "the cache policy is read-allocate".
This paragraph does not specify the cache's general policy, only a read policy, and only the *read allocation* policy. Its write policies are not defined or even constrained by this paragraph.
Based on the cache line allocation policies described in section 12.3.3 in the arm developers guide, my interpretation of 'allocate on read-miss' was as above.
The ARM926EJ-S is "allocate on read-miss" as well as "allocate on write-miss"; and none of its write policies bypasses the cache.
-sughosh
Amicalement,