2 Oct
2013
2 Oct
'13
10:36 a.m.
Hi Fabio,
On 30/09/2013 18:16, Fabio Estevam wrote:
Enable L2 cache for improving the system performance.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index fc7c767..e4cd85c 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif
mcr 15, 1, r0, c9, c0, 2
- /* enable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- orr r0, r0, #2
- mcr 15, 0, r0, c1, c0, 1
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
This is a repost from a your previous patch on August, 19th, where you report slow tftp transfer even with L2-cache enable. Was this issue solved or it is completeley unrelated to the cache ?
Best regards, Stefano
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