On Tuesday 29 April 2008, kenneth johansson wrote:
Stefan already asked this... I would also like to understand why the data cache cannot be used for initial RAM as we do on so many other systems?
Agreed. The changes were based on the comments in the Kilauea and Makalu board ports indicating that this had been attempted--twice--and didn't work.
I am escalating with AMCC to find out if this is a processor errata, board issue or just a programming issue that needs to be investigated further.
The cache trick works fine on 405CR/405GP. Is the cache redesigned for 405EX. Why would they still call it a 405 if the core was redesigned?
I already sent an update to Grant privately on this. Here again:
The main problem is that the board crashes with an exception (0x200: Data machine check) when init RAM in dcache is used. This happens upon calling trap_init() in board_init_r(). The exception must be pending and is "activated" upon the trap_init() call. Either Grant (or somebody else?) will look into this, or I will try to look into is (again) in a few days.
Thanks.
Best regards, Stefan
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