2 Jun
2023
2 Jun
'23
7:47 a.m.
On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:
Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.co...
Signed-off-by: William Zhang william.zhang@broadcom.com
Reviewed-by: Jagan Teki jagan@amarulasolutions.com