Hi Richard,
Pasting some of the discussions we had over IRC for completeness.
On Tue, 12 Mar 2024 at 19:00, Richard Henderson richard.henderson@linaro.org wrote:
On 3/12/24 04:08, Ilias Apalodimas wrote:
index 33f4624b561d..ccdd1966cfbc 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -132,7 +132,7 @@ SECTIONS
_end = .;
.bss ALIGN(8): {
.bss : { __bss_start = .; *(.bss*) __bss_end = .;The code in arch/arm/lib/crt0_64.S assumes __bss_end - __bss_start is a multiple of 8. But that could probably be replaced by a proper call to memset fairly easily.
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index b6b19a4174fe..a9fcbbf22e96 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -155,7 +155,7 @@ SECTIONS
__image_copy_end = .;
.rel.dyn ALIGN(4) : {
.rel.dyn : { __rel_dyn_start = .; *(.rel*) __rel_dyn_end = .;Because of the overlay, this affects .bss too.
The code in arch/arm/lib/crt0.S may or may not be configured to use memset. When it isn't, it requires __bss_end - __bss_start to be a multiple of 4. Why does this not always use memset?
I think it's due to size restrictions in SPL. Since I can't test all affected platforms, I prefer leaving it as is at least for now. I'll explicitly align sections to 4/8 bytes in v3. Once we get this merged we can try and clean those up as you suggested on a followup patchset
Thanks /Ilias
r~