Re: [PATCH 15/31] rockchip: rk3399: Sync soc device tree from linux v6.8

Hi Jonas,

On 3/31/24 22:28, Jonas Karlman wrote:

Sync RK3399 SoC common .dtsi-files from linux v6.8.

The ethernet0 alias is removed from rk3399.dtsi in this patch, it will be restored in board specific .dts-files. There is no other intended

Please add ethernet0 alias to rk3399-u-boot.dtsi and remove it in the patch that moves it to board-specific dts files so that this is not a breaking change and we can bisect through this patch if we need to :)

change with this patch.

Could you please mention that rng node is named crypto1 in Linux DT? The diff here was a bit surprising since rng node is entirely removed.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-u-boot.dtsi | 52 ++-- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- 5 files changed, 308 insertions(+), 74 deletions(-)

diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi index 69cc9b05baa5..783120e9cebe 100644 --- a/arch/arm/dts/rk3399-op1-opp.dtsi +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -4,7 +4,7 @@ */

/ {

• cluster0_opp: opp-table0 {

• cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;

@@ -39,7 +39,7 @@ }; };

• cluster1_opp: opp-table1 {

• cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;

@@ -82,7 +82,7 @@ }; };

• gpu_opp_table: opp-table2 {

• gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";

  opp00 {

@@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; };

• dmc_opp_table: opp-table-3 {

• compatible = "operating-points-v2";
  

• opp00 {
  

• 	opp-hz = /bits/ 64 <400000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp01 {
  

• 	opp-hz = /bits/ 64 <666000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp02 {
  

• 	opp-hz = /bits/ 64 <800000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp03 {
  

• 	opp-hz = /bits/ 64 <928000000>;
  

• 	opp-microvolt = <925000>;
  

• };
  

• }; };

  &cpu_l0 {

@@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; };

+&dmc {

• operating-points-v2 = <&dmc_opp_table>;

+};

• &gpu { operating-points-v2 = <&gpu_opp_table>; };

diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index da41cd81ebb7..fee5e7111279 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -4,7 +4,7 @@ */

/ {

• cluster0_opp: opp-table0 {

• cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;

@@ -35,7 +35,7 @@ }; };

• cluster1_opp: opp-table1 {

• cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;

@@ -74,7 +74,7 @@ }; };

• gpu_opp_table: opp-table2 {

• gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";

  opp00 {

diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index b8f95b86d86b..dcfcec4f3072 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"

-&rng {

• status = "okay";

-};

• &sdhci { max-frequency = <25000000>; };

diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index adb64d17e040..d2648abd0a44 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -2,8 +2,6 @@ /*

• Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com

*/ -#define USB_CLASS_HUB 9

• #include "rockchip-u-boot.dtsi"

  / {

@@ -24,44 +22,11 @@ reg = <0x0 0xff620000 0x0 0x100>; };

• dfi: dfi@ff630000 {

• bootph-all;
  

• reg = <0x00 0xff630000 0x00 0x4000>;
  

• compatible = "rockchip,rk3399-dfi";
  

• rockchip,pmu = <&pmugrf>;
  

• clocks = <&cru PCLK_DDR_MON>;
  

• clock-names = "pclk_ddr_mon";
  

• };
• rng: rng@ff8b8000 {

• compatible = "rockchip,rk3399-crypto";
  

• reg = <0x0 0xff8b8000 0x0 0x1000>;
  

• status = "okay";
  

• };
• dmc: dmc {

• bootph-all;
  

• compatible = "rockchip,rk3399-dmc";
  

• devfreq-events = <&dfi>;
  

• interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru SCLK_DDRC>;
  

• clock-names = "dmc_clk";
  

• reg = <0x0 0xffa80000 0x0 0x0800
  

•        0x0 0xffa80800 0x0 0x1800
  

•        0x0 0xffa82000 0x0 0x2000
  

•        0x0 0xffa84000 0x0 0x1000
  

•        0x0 0xffa88000 0x0 0x0800
  

•        0x0 0xffa88800 0x0 0x1800
  

•        0x0 0xffa8a000 0x0 0x2000
  

•        0x0 0xffa8c000 0x0 0x1000>;
  

• };
• pmusgrf: syscon@ff330000 { bootph-all;

I have my doubts the PMU SGRF is accessible from U-Boot proper if TF-A loads it into normal world. Maybe this should rather be bootph-pre-sram+bootph-pre-ram?

Nothing to fix in this series though.

compatible = "rockchip,rk3399-pmusgrf", "syscon";
reg = <0x0 0xff330000 0x0 0xe3d4>;

};

• };

  #if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)

@@ -93,6 +58,19 @@ bootph-all; };

+&dmc {

• bootph-all;
• reg = <0x0 0xffa80000 0x0 0x0800

•       0x0 0xffa80800 0x0 0x1800
  

•       0x0 0xffa82000 0x0 0x2000
  

•       0x0 0xffa84000 0x0 0x1000
  

•       0x0 0xffa88000 0x0 0x0800
  

•       0x0 0xffa88800 0x0 0x1800
  

•       0x0 0xffa8a000 0x0 0x2000
  

•       0x0 0xffa8c000 0x0 0x1000>;
  

• status = "okay";

+};

Missing bootph-all for dfi?

[...]

Cheers, Quentin