diff --git a/MAKEALL b/MAKEALL index bb09627..aca53ed 100755 --- a/MAKEALL +++ b/MAKEALL @@ -524,6 +524,7 @@ LIST_SA=" \ gcplus \ lart \ shannon \ + jornada \ " ######################################################################### diff --git a/Makefile b/Makefile index 1445e8b..a75d581 100644 --- a/Makefile +++ b/Makefile @@ -2669,6 +2669,9 @@ lart_config : unconfig shannon_config : unconfig @$(MKCONFIG) $(@:_config=) arm sa1100 shannon +jornada_config : unconfig + @$(MKCONFIG) $(@:_config=) arm sa1100 jornada + ######################################################################### ## ARM92xT Systems ######################################################################### diff --git a/board/jornada/Makefile b/board/jornada/Makefile new file mode 100644 index 0000000..1b4e192 --- /dev/null +++ b/board/jornada/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# 2004 (c) MontaVista Software, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := jornada.o +SOBJS := setup.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/jornada/config.mk b/board/jornada/config.mk new file mode 100644 index 0000000..74cb419 --- /dev/null +++ b/board/jornada/config.mk @@ -0,0 +1,7 @@ +# +# SA-1110 based Intel Assabet board +# +# The Intel Assabet 1 bank of 32 MiB SDRAM +# + +TEXT_BASE = 0xc1f00000 diff --git a/board/jornada/jornada.c b/board/jornada/jornada.c new file mode 100644 index 0000000..dfaca1d --- /dev/null +++ b/board/jornada/jornada.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +static inline u8 +readb(volatile u8 * p) +{ + return *p; +} + +static inline void +writeb(u8 v, volatile u8 * p) +{ + *p = v; +} + +static void jornada_init(void) +{ + +PPSR &= ~(GPIO_GPIO10 | GPIO_GPIO7); +PPDR |= (GPIO_GPIO10 | GPIO_GPIO7); + +PPSR |= GPIO_GPIO10; +} + +int board_init(void) +{ + char *s = getenv("serial#"); + + serial_puts("hope we see this\n"); + + gd->bd->bi_arch_number = 48; + gd->bd->bi_boot_params = 0xc0000100; + + jornada_init(); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/jornada/setup.S b/board/jornada/setup.S new file mode 100644 index 0000000..7289ba7 --- /dev/null +++ b/board/jornada/setup.S @@ -0,0 +1,226 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/*----------------------------------------------------------------------- + * Board defines: + */ + +#define MDCNFG 0x00 +#define MDCAS00 0x04 +#define MDCAS01 0x08 +#define MDCAS02 0x0C +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 +#define MDREFR 0x1C +#define MDCAS20 0x20 +#define MDCAS21 0x24 +#define MDCAS22 0x28 +#define MSC2 0x2C +#define SMCNFG 0x30 + +#define MDCNFG_BANK0_ENABLE (1 << 0) +#define MDCNFG_DTIM0_SDRAM (1 << 2) +#define MDCNFG_DWID0_32B (0 << 3) +#define MDCNFG_DRAC0(n_) (((n_) & 7) << 4) +#define MDCNFG_TRP0(n_) (((n_) & 0xF) << 8) +#define MDCNFG_TDL0(n_) (((n_) & 3) << 12) +#define MDCNFG_TWR0(n_) (((n_) & 3) << 14) +#define MSC_RT_ROMFLASH 0 +#define MSC_RBW32 (0 << 2) +#define MSC_RDF(n_) (((n_) & 0x1f) << 3) +#define MSC_RDN(n_) (((n_) & 0x1f) << 8) +#define MSC_RRR(n_) (((n_) & 0x07) << 13) +#define MSC_RT_VARLAT_345 1 +#define MDREFR_TRASR(n_) (n_ & (0x0000000f)) +#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4) +#define MDREFR_K0RUN (1 << 17) +#define MDREFR_K0DB2 (1 << 18) +#define MDREFR_K1RUN (1 << 21) +#define MDREFR_K1DB2 (1 << 22) +#define MDREFR_K2RUN (1 << 25) +#define MDREFR_K2DB2 (1 << 26) +#define MDREFR_SLFRSH (1 << 31) +#define MDREFR_E1PIN (1 << 20) +#define PSSR_DH 0x00000008 +#define PSSR 0x04 +#define PM_BASE 0x90020000 + +#define mdcnfg_1 (MDCNFG_BANK0_ENABLE|MDCNFG_DTIM0_SDRAM|MDCNFG_DWID0_32B|MDCNFG_DRAC0(6)|MDCNFG_TRP0(2)|MDCNFG_TDL0(3)|MDCNFG_TWR0(1)) +#define cs0_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(15)|MSC_RDN(15)|MSC_RRR(2)) +#define cs1_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7)) +#define cs2_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7)) +#define cs3_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7)) +#define cs4_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(11)|MSC_RDN(9)|MSC_RRR(1)) +#define cs5_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(3)|MSC_RDN(0)|MSC_RRR(1)) +#define msc0_1 (cs0_1|(cs1_1 << 16)) +#define msc1_1 (cs2_1|(cs3_1 << 16)) +#define msc2_1 (cs4_1|(cs5_1 << 16)) + +#define ICMR 0x04 +#define PPCR 0x14 +/*----------------------------------------------------------------------- + * Setup parameters for the board: + */ +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 +PWR_BASE: .word 0x90020000 +GPIO_BASE: .long 0x90040000 +IC_BASE: .word 0x90050000 + +cpuspeed: .word 0xa0 +/* calculated from old blob bootloader */ +mdcnfg: .long 0x00007255 /* mdcnfg 0x00007255 */ +mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */ +mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */ +mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */ +msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */ +msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */ +mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */ +mdrefr: .long 0x04340327 /* mdrefr 0x04340327 */ +mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */ +mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */ +mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */ +msc2: .long 0x201d2959 /* msc2 0x201d2959 */ +smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */ + +.globl lowlevel_init +lowlevel_init: + + /* Setting up the memory and stuff */ + /***********************************/ + + ldr r0, MEM_BASE + + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + ldr r1, mdcas00 + str r1, [r0, #MDCAS00] + + ldr r1, mdcas01 + str r1, [r0, #MDCAS01] + + ldr r1, mdcas02 + str r1, [r0, #MDCAS02] + + ldr r1, mdcas20 + str r1, [r0, #MDCAS20] + + ldr r1, mdcas21 + str r1, [r0, #MDCAS21] + + ldr r1, mdcas22 + str r1, [r0, #MDCAS22] + + ldr r2, [r0, #MDREFR] + bic r2, r2, #MDREFR_K0DB2 + bic r2, r2, #MDREFR_K1DB2 + bic r2, r2, #MDREFR_K2DB2 + str r2, [r0, #MDREFR] + + ldr r2, [r0, #MDREFR] + orr r2, #MDREFR_TRASR(7) + + mov r4, #0x2000 + spin: + subs r4, r4, #1 + bne spin + + ldr r1, PWR_BASE + mov r2, #PSSR_DH + str r2, [r1, #PSSR] + + + /* clear KxDB2 */ + ldr r2, [ r0, #MDREFR] + bic r2, r2, #MDREFR_K0DB2 + bic r2, r2, #MDREFR_K1DB2 + bic r2, r2, #MDREFR_K2DB2 + str r2, [ r0, #MDREFR] + +/* set TRASR and DRI, KxDB2 */ + ldr r2, [r0, #MDREFR] + orr r2, r2, #MDREFR_TRASR(7) + orr r2, r2, #MDREFR_DRI(12) + orr r2, r2, #MDREFR_K0DB2 + orr r2, r2, #MDREFR_K1DB2 + orr r2, r2, #MDREFR_K2DB2 + str r2, [r0, #MDREFR] + +/* set KxRUN */ + ldr r2, [ r0, #MDREFR ] + orr r2, r2, #MDREFR_K0RUN + orr r2, r2, #MDREFR_K1RUN + orr r2, r2, #MDREFR_K2RUN + str r2, [r0, #MDREFR] + + /* clear SLFRESH */ + ldr r2, [r0, #MDREFR] + bic r2, r2, #MDREFR_SLFRSH + str r2, [r0, #MDREFR] + + /* toggle E1PIN (set -> clear) */ + ldr r2, [r0, #MDREFR] + orr r2, r2, #MDREFR_E1PIN + str r2, [r0, #MDREFR] + + ldr r1, MEM_START +.rept 8 + ldr r0, [r1] +.endr + + ldr r2, [r0, #MDCNFG] + orr r2, r2, #0x00000003 + orr r2, r2, #0x00030000 + str r2, [r0, #MDCNFG] + + ldr r1, msc0 + str r1, [r0, #MSC0] + + ldr r1, msc1 + str r1, [r0, #MSC1] + + ldr r1, msc2 + str r1, [r0, #MSC2] + + ldr r1, smcnfg + str r1, [r0, #SMCNFG] + + ldr r1, mecr + str r1, [r0, #MECR] + + /* load something to activate bank */ + ldr r1, MEM_START + + /* done */ + mov pc, lr + diff --git a/board/jornada/u-boot.lds b/board/jornada/u-boot.lds new file mode 100644 index 0000000..de6101e --- /dev/null +++ b/board/jornada/u-boot.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/include/configs/jornada.h b/include/configs/jornada.h new file mode 100644 index 0000000..23acc4f --- /dev/null +++ b/include/configs/jornada.h @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2004 (c) MontaVista Software, Inc. + * + * Configuation settings for the Intel Assabet board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ +#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */ + +#undef CONFIG_USE_IRQ + +#define CONFIG_SKIP_LOWLEVEL_INIT 1 + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + +/* Console setting */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ + +/* + * select serial console configuration + */ +#define CONFIG_SA1100_SERIAL 1 +#define CONFIG_SERIAL3 1 /* we use serial 3 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_IS_IN_FLASH 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTARGS "console=ttySA0,115200n8" +#define CONFIG_BOOTCOMMAND "bootp;bootm" +#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "HP Jornada # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)/* Print Buffer Size */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* reserve 128kb for monitor */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default adress to load kernel */ +#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + * + * We got x banks with a total of 128MB Sdram. + * + * + * + * + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 bank of SDRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x04000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors */ + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_RAMSTART +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE +#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ +#undef CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_ENV_IN_OWN_SECTOR 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE + +#endif /* __CONFIG_H */