Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII- 1000 mode.
Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- drivers/qe/qe.c | 13 +++++++++++-- drivers/qe/qe.h | 1 - include/asm-ppc/immap_qe.h | 3 +++ 3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index a8e9399..6232c85 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -108,14 +108,23 @@ static void qe_sdma_init(void) out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT)); }
-static u8 thread_snum[QE_NUM_OF_SNUM] = { +/* This table is a list of the serial numbers of the Threads, taken from the + * "SNUM Table" chart in the QE Reference Manual. The order is not important, + * we just need to know what the SNUMs are for the threads. + */ +static u8 thread_snum[] = { 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, 0x34, 0x35, 0x88, 0x89, 0x98, 0x99, 0xa8, 0xa9, 0xb8, 0xb9, 0xc8, 0xc9, - 0xd8, 0xd9, 0xe8, 0xe9 + 0xd8, 0xd9, 0xe8, 0xe9, + 0x08, 0x09, 0x18, 0x19, + 0x28, 0x29, 0x38, 0x39, + 0x48, 0x49, 0x58, 0x59, + 0x68, 0x69, 0x78, 0x79, + 0x80, 0x81 };
static void qe_snums_init(void) diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index 1eb0a74..d4ccec0 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -25,7 +25,6 @@
#include "common.h"
-#define QE_NUM_OF_SNUM 28 #define QE_NUM_OF_BRGS 16 #define UCC_MAX_NUM 8
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 7613b5c..1446734 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -609,10 +609,13 @@ extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8323) #define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_MPC8569) #define MAX_QE_RISC 4 +#define QE_NUM_OF_SNUM 46 #else #define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 #endif
#endif /* __IMMAP_QE_H__ */