Re: [PATCH v1 2/5] riscv: dts: jh7110: Add PLL clock controller node

On Fri, Jul 07, 2023 at 06:50:08PM +0800, Hal Feng wrote:

From: Xingyu Wu xingyu.wu@starfivetech.com

Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com Signed-off-by: Hal Feng hal.feng@starfivetech.com

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arch/riscv/dts/jh7110.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com