On Monday 19 May 2008, Grant Erickson wrote:
And I'm wondering if this code really should go into this file "44x_spd_ddr2.c". Since now a 405 variant (405EX) can use this code too we should probably change the name to "4xx_spd_ddr2.c". And with this new fixed DDR2 init code it the SPD is not really fitting anymore. So the new name should probably be "4xx_ddr2.c".
Comments welcome.
This controller works with both DDR and DDR2 memories, so that might be misleading.
Right. But we need to differentiate from the "DDR only" controller used on 440GP/GX/EP/GR.
What I'd like to see is a move away from processor-based CONFIG_ and towards feature-based CONFIG_. In that way, we can avoid ever-growing lists like:
#if defined(CONFIG_PPCX) || defined(CONFIG_PPCY) ||defined(CONFIG_PPCZ)
Full ack.
However, what's needed then are convenient mnemonics for various cores/blocks. EMAC works well enough for that block. However, DDR/DDR2/SDRAM seem too generic. Does AMCC call this block something internally that's leaked out? I see "Denali" used for one memory controller core, correct? Or is that a board name?
Denali is the name of the DDR(2) controller core IP supplier used on 440EPx etc. Since the "other" DDR(2) controller core comes from IBM, we should probably name it "4xx_ibm_ddr2.c". Not sure about ddr2 vs. ddr though.
Best regards, Stefan
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