I've seen one thread on this subject http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/19224 and tried to repeat the same trick.
1. I have updated (latest snapshot) u-boot:
include/configs/MPC8260ADS.h
#define CFG_HRCW_MASTER 0x0e72b605
board/mpc8260ads/config.mk
TEXT_BASE = 0xff800000
2. Using BDI2000 (MPC8272ADS JP9 is configured to take Hard Reset Configuration source from BCSR - otherwise board keep reseting) 8272>load 8272>unlock 0xff800000 0x40000 32 8272>erase 0xFF800000 BLOCK 8272>prog 0xFF800000 u-boot.bin BIN
3. Change JP9 to take Hard Reset Configuration from FLASH (SW2 Boot Source is FLASH)
After power cycling BDI and board - the board keep reseting (BDI is attached to the board). Yes, 0xFFF00100 is not valid breakpoint anymore - I guess it should be something like 0x00000100. But I suspect even I got u-boot wrong BDI still should "freeze" the board instead of reseting. Is anyone got BDI and u-boot working on MPC8272ADS in low boot mode? Any help is really appreciated. Below is output of BDI while reseting and BDI init from config file.
... *** TARGET: reset detected, restarting target - BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x00000001 => 0x00000001 - JTAG exists check passed - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - Target PVR is 0x80822014 - Target SVR is 0x00000000 - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI sets breakpoint at 0xFFF00100 - BDI resumes program execution - Waiting for target stop passed - TARGET: Target PVR is 0x80822014 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed
Here is the init core from BDI config:
[INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI WM32 0x0F010004 0xFFFFFFC3 ;SYPCR: disable watchdog WM32 0x0F0101A8 0x04700000 ;IMMR : internal space @ 0x04700000 WM32 0x04710024 0x100C0000 ;BCR : Single PQ2, .. WM32 0x04710c94 0x00000001 ;RMR : checkstop reset enable ; ; init memory controller WM32 0x04710104 0xFF800876 ;OR0: Flash 8MB, CS early negate, 11 w.s., Timing relax WM32 0x04710100 0xFF801801 ;BR0: Flash @0xFF800000, 32bit, no parity WM32 0x0471010C 0xFFFF8010 ;OR1: BCSR 32KB, all types access, 1 w.s. WM32 0x04710108 0x04501801 ;BR1: BCSR @0x04500000, 32bit, no parity WM32 0x04710124 0xFFFF8866 ;OR4: EEPROM 32KB, all types access, 6 w.s. WM32 0x04710120 0xC2000801 ;BR4: EEPROM @0xC2000000, 8bit, no parity ; ; init SDRAM Init (PPC bus) WM16 0x04710184 0x2800 ;MPTPR: Divide Bus clock by 41 WM8 0x0471019C 0x13 ;PSRT : Divide MPTPR output by 20 WM32 0x04710114 0xfe002ec0 ;OR2 : 32MB, 2 banks, row start at A9, 11 rows WM32 0x04710110 0x00000041 ;BR2 : SDRAM @0x00000000, 64bit, no parity WM32 0x04710190 0x824b36a3 ;PSDMR: Precharge all banks WM32 0x04710190 0xaa4b36a3 WM8 0x00000000 0x00 ;Access SDRAM WM32 0x04710190 0x8a4b36a3 ;PSDMR: CBR Refresh WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM8 0x00000000 0xFF ;Access SDRAM WM32 0x04710190 0x9a4b36a3 ;PSDMR: Mode Set WM8 0x00000190 0x00 ;Access SDRAM WM32 0x04710190 0xc24b36a3 ;PSDMR: enable refresh, normal operation