rick@andestech.com 於 2018年11月1日 週四 下午12:13寫道：
RISC-V does not guarantee that stores to instruction memory are visible to instruction fetches (i.e. incoherent instruction caches). Invalidate the instruction cache to ensure the kernel function pointer points to the correct memory location.
Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
Changes in v2:
- Clarify reasoning behind patch in commit message
arch/riscv/lib/bootm.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 2b5ccce933..c1cf618806 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -40,6 +40,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) return 1;
kernel = (void (*)(ulong, void *))images->ep;
invalidate_icache_all();
Hi Lukas
[PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable] will implement
+void cache_flush(void) { + invalidate_icache_all(); + flush_dcache_all(); }
It seem redundant here.
Rick
bootstage_mark(BOOTSTAGE_ID_RUN_OS);-- 2.17.2