This patch adds clkgate node for mt7628 and adds clock gate property for usb phy node.
Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/mt7628a.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 0e2b6598ea..dd11cac28c 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clk/mt7628-clk.h> #include <dt-bindings/reset/mt7628-reset.h>
/ { @@ -44,6 +45,12 @@ mask = <0x1>; };
+ clkgate: clkgate@0x30 { + reg = <0x30 0x4>; + compatible = "mediatek,mtmips-clk-gate"; + #clock-cells = <1>; + }; + rstctrl: rstctrl@0x34 { reg = <0x34 0x4>; compatible = "mediatek,mtmips-reset"; @@ -357,6 +364,9 @@ ralink,sysctl = <&sysc>; resets = <&rstctrl MT7628_UPHY_RST>; reset-names = "phy"; + + clocks = <&clkgate MT7628_UPHY_CLK>; + clock-names = "cg"; };
ehci@101c0000 {