Signed-off-by: Julien May mailinglist@miromico.ch --- MAKEALL | 1 + Makefile | 3 + board/miromico/hammerhead/Makefile | 40 +++++++ board/miromico/hammerhead/config.mk | 3 + board/miromico/hammerhead/eth.c | 37 ++++++ board/miromico/hammerhead/hammerhead.c | 105 +++++++++++++++++ board/miromico/hammerhead/u-boot.lds | 73 ++++++++++++ cpu/at32ap/at32ap700x/gpio.c | 11 ++ cpu/at32ap/at32ap700x/sm.h | 2 +- cpu/at32ap/cpu.c | 5 + include/asm-avr32/arch-at32ap700x/clk.h | 1 + include/asm-avr32/arch-at32ap700x/gpio.h | 3 + include/configs/hammerhead.h | 179 ++++++++++++++++++++++++++++++ net/eth.c | 4 + 14 files changed, 466 insertions(+), 1 deletions(-) create mode 100644 board/miromico/hammerhead/Makefile create mode 100644 board/miromico/hammerhead/config.mk create mode 100644 board/miromico/hammerhead/eth.c create mode 100644 board/miromico/hammerhead/hammerhead.c create mode 100644 board/miromico/hammerhead/u-boot.lds create mode 100644 include/configs/hammerhead.h
diff --git a/MAKEALL b/MAKEALL index f40de23..89b68a5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -699,6 +699,7 @@ LIST_avr32=" \ atstk1004 \ atstk1006 \ atngw100 \ + hammerhead \ "
######################################################################### diff --git a/Makefile b/Makefile index 154e592..09bae45 100644 --- a/Makefile +++ b/Makefile @@ -2885,6 +2885,9 @@ atstk1006_config : unconfig atngw100_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x
+hammerhead_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap hammerhead miromico at32ap700x + ######################################################################### ######################################################################### ######################################################################### diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile new file mode 100644 index 0000000..c5fc67a --- /dev/null +++ b/board/miromico/hammerhead/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2008 Miromico AG +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o eth.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/miromico/hammerhead/config.mk b/board/miromico/hammerhead/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/miromico/hammerhead/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/miromico/hammerhead/eth.c b/board/miromico/hammerhead/eth.c new file mode 100644 index 0000000..969c48e --- /dev/null +++ b/board/miromico/hammerhead/eth.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Ethernet initialization for the Miromico Hammerhead AVR32 board + * + * Mostly copied form Atmel ATNGW100 sources + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/arch/memory-map.h> + +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#ifdef CONFIG_CMD_NET +void board_eth_initialize(bd_t *bi) +{ + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); +} +#endif diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c new file mode 100644 index 0000000..69ff7fa --- /dev/null +++ b/board/miromico/hammerhead/hammerhead.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Mostly copied form atmel ATNGW100 sources + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "../cpu/at32ap/at32ap700x/sm.h" + +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + gpio_enable_ebi(); + gpio_enable_usart1(); + +#if defined(CONFIG_MACB) + gpio_enable_macb0(); +#endif +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + + /* Select GCLK3 peripheral function. We'll need it as clock output + * for ethernet PHY. */ + gpio_enable_gclk3(); + return 0; +} + +long int initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %u of %u MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x01; +} + +void gclk_init(void) +{ + /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ + + /* Enable GCLK3 with no input divider, from OSC0 (crystal) */ + sm_writel( PM_GCCTRL(3), SM_BIT(CEN) ); +} diff --git a/board/miromico/hammerhead/u-boot.lds b/board/miromico/hammerhead/u-boot.lds new file mode 100644 index 0000000..e736adf --- /dev/null +++ b/board/miromico/hammerhead/u-boot.lds @@ -0,0 +1,73 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 859124a..2b7717f 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -142,3 +142,14 @@ void gpio_enable_mmci(void) gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ } #endif + +/* + * Hammerhead board uses GCLK3 (Periph A on PB29) as 25MHz clock output + * for ethernet PHY. + */ +void __gpio_enable_gclk3(void) +{ + gpio_select_periph_A(GPIO_PIN_PB29, 0); /* GCLK3 */ +} + +void gpio_enable_gclk3(void) __attribute__((weak, alias("__gpio_enable_gclk3"))); diff --git a/cpu/at32ap/at32ap700x/sm.h b/cpu/at32ap/at32ap700x/sm.h index 6492c8e..b6e4409 100644 --- a/cpu/at32ap/at32ap700x/sm.h +++ b/cpu/at32ap/at32ap700x/sm.h @@ -21,7 +21,7 @@ #define SM_PM_IMR 0x0048 #define SM_PM_ISR 0x004c #define SM_PM_ICR 0x0050 -#define SM_PM_GCCTRL 0x0060 +#define SM_PM_GCCTRL(x) (0x0060 + 4 * x) #define SM_RTC_CTRL 0x0080 #define SM_RTC_VAL 0x0084 #define SM_RTC_TOP 0x0088 diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 0ba8361..4a92aab 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -65,6 +65,11 @@ int cpu_init(void) sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
+ if(gclk_init) + { + gclk_init(); + } + return 0; }
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index 4a1dd33..63671db 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -76,6 +76,7 @@ static inline unsigned long get_mci_clk_rate(void) #endif
extern void clk_init(void); +extern void gclk_init(void) __attribute__((weak));
/* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index b10a3e4..c350d54 100644 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -216,5 +216,8 @@ void gpio_enable_macb1(void); #ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void); #endif +#ifdef CONFIG_HAMMERHEAD +void gpio_enable_gclk3(void); +#endif
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h new file mode 100644 index 0000000..6699aea --- /dev/null +++ b/include/configs/hammerhead.h @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Configuration settings for the Miromico Hammerhead AVR32 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_HAMMERHEAD 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 25000000 /* 25MHz crystal */ +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 5 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 + +#define CONFIG_HOSTNAME hammerhead + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet address + * should be generated and assigned to the environment variables + * "ethaddr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + CFG_SDRAM_BASE + gd->sdram_size; \ + }) +#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) + +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff --git a/net/eth.c b/net/eth.c index c4f24c6..054a9fd 100644 --- a/net/eth.c +++ b/net/eth.c @@ -65,6 +65,7 @@ extern int atngw100_eth_initialize(bd_t *); extern int mcffec_initialize(bd_t*); extern int mcdmafec_initialize(bd_t*); extern int at91sam9_eth_initialize(bd_t *); +extern int board_eth_initialize(bd_t *);
#ifdef CONFIG_API extern void (*push_packet)(volatile void *, int); @@ -291,6 +292,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) at91sam9_eth_initialize(bis); #endif +#if defined(CONFIG_HAMMERHEAD) + board_eth_initialize(bis); +#endif
if (!eth_devices) { puts ("No ethernet found.\n");