
7 Mar
2023
7 Mar
'23
2:34 p.m.
po 27. 2. 2023 v 18:17 odesÃlatel Jiajie Chen c@jia.je napsal:
It was incorrectly using an old priv->regs pointer, which was initialized to zero. SPI resets won't happen on first call.
Signed-off-by: Jiajie Chen c@jia.je
drivers/spi/xilinx_spi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 4e9115dafe..9e6255a172 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -112,10 +112,9 @@ struct xilinx_spi_priv { static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
struct xilinx_spi_regs *regs;
regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); writel(SPISSR_RESET_VALUE, ®s->srr);
-- 2.30.2
Applied. M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs