
30 Jun
2016
30 Jun
'16
7:40 p.m.
"Andre" == Andre Przywara andre.przywara@arm.com writes:
Hi,
I really don't know. This simple bug has cost me at least two hours yesterday, since it was the rather innocent access to a variable that caused the issue. And if it wouldn't have been for Siarhei to point me in the right direction I'd have spend even more time to find a fix.
Agreed. The toolchain will complain loudly about an overflow of SRAM space, but not about BSS access before DRAM is available.
--
Bye, Peter Korsgaard