Hi Stefan,
On Tue, Aug 23, 2016 at 10:54 PM, Chris Packham judge.packham@gmail.com wrote:
On Tue, Aug 23, 2016 at 6:57 PM, Stefan Roese sr@denx.de wrote:
Hi Chris,
On 22.08.2016 02:38, Chris Packham wrote:
From: Chris Packham chris.packham@alliedtelesis.co.nz
Add pin control settings for the NAND flash interface. This interface is multiplexed with the device bus interface to the function is "dev" not "nand" as one might expect.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz Cc: Luka Perkov luka.perkov@sartura.hr Cc: Dirk Eibach eibach@gdsys.de
I don't think this is strictly necessary. A quick scan of boards that use this family of processor all seem to set their MPP configurations manually.
Correct. Unfortunately we don't have a pin-ctrl driver for AXP / A38x in U-Boot yet. Such a driver would be very welcome though. ;)
Another issue is that technically on the Armada-385 there are 4 possible CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26, mpp27 and mpp6 are all potentially available. I guess if any boards actually use them they can add them to their pin specification. At the very least such boards would need to update the num-cs property anyway.
How is this handled in the kernel?
I haven't seen anything in the kernel yet that uses these chip selects.
I would very much like to see these changes in the dts in sync with the kernel as much as possible. Does the kernel also use "dev" instead of "nand" here?
Yes I based this on https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar... I haven't got round to porting the kernel to my board so I imagine a similar change will be required to armada-38x.dtsi in the kernel.
I've sent a kernel patch for the armada-38x[1] so perhaps we should just drop this one and sync up if/when the kernel patch is accepted.
[1] - http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/451027.htm...