[U-Boot] [PATCH 1/5] 85xx: Convert CONFIG_SYS_{PCI, RIO}_MEM_BASE to _MEM_BUS for FSL boards

2 Dec 2008

Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
---
 board/freescale/mpc8536ds/mpc8536ds.c   |   20 ++++++++++----------
 board/freescale/mpc8540ads/law.c        |    2 +-
 board/freescale/mpc8540ads/tlb.c        |    4 ++--
 board/freescale/mpc8544ds/mpc8544ds.c   |   26 +++++++++++++-------------
 board/freescale/mpc8548cds/mpc8548cds.c |    4 ++--
 board/freescale/mpc8548cds/tlb.c        |    4 ++--
 board/freescale/mpc8560ads/law.c        |    2 +-
 board/freescale/mpc8560ads/tlb.c        |    4 ++--
 board/freescale/mpc8568mds/law.c        |    2 +-
 board/freescale/mpc8568mds/mpc8568mds.c |    4 ++--
 board/freescale/mpc8572ds/mpc8572ds.c   |    6 +++---
 cpu/mpc85xx/pci.c                       |   16 ++++++++++++----
 include/configs/MPC8536DS.h             |   16 ++++++++--------
 include/configs/MPC8540ADS.h            |    8 ++++----
 include/configs/MPC8541CDS.h            |    8 ++++----
 include/configs/MPC8544DS.h             |   20 ++++++++++----------
 include/configs/MPC8548CDS.h            |   14 +++++++-------
 include/configs/MPC8555CDS.h            |    8 ++++----
 include/configs/MPC8560ADS.h            |    8 ++++----
 include/configs/MPC8568MDS.h            |   10 +++++-----
 include/configs/MPC8572DS.h             |   12 ++++++------
 21 files changed, 103 insertions(+), 95 deletions(-)

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index b2c37f0..1636404 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -204,7 +204,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE,
+			       CONFIG_SYS_PCIE3_MEM_BUS,
    		       CONFIG_SYS_PCIE3_MEM_PHYS,
    		       CONFIG_SYS_PCIE3_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -259,7 +259,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
    		       CONFIG_SYS_PCIE1_MEM_PHYS,
    		       CONFIG_SYS_PCIE1_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -271,10 +271,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCIE1_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_BUS2,
    		       CONFIG_SYS_PCIE1_MEM_PHYS2,
    		       CONFIG_SYS_PCIE1_MEM_SIZE2,
    		       PCI_REGION_MEM);
@@ -322,7 +322,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE,
+			       CONFIG_SYS_PCIE2_MEM_BUS,
    		       CONFIG_SYS_PCIE2_MEM_PHYS,
    		       CONFIG_SYS_PCIE2_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -334,10 +334,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCIE2_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE2,
+			       CONFIG_SYS_PCIE2_MEM_BUS2,
    		       CONFIG_SYS_PCIE2_MEM_PHYS2,
    		       CONFIG_SYS_PCIE2_MEM_SIZE2,
    		       PCI_REGION_MEM);
@@ -390,7 +390,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
    		       CONFIG_SYS_PCI1_MEM_PHYS,
    		       CONFIG_SYS_PCI1_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -402,10 +402,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCI1_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCI1_MEM_BASE2
+#ifdef CONFIG_SYS_PCI1_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE2,
+			       CONFIG_SYS_PCI1_MEM_BUS2,
    		       CONFIG_SYS_PCI1_MEM_PHYS2,
    		       CONFIG_SYS_PCI1_MEM_SIZE2,
    		       PCI_REGION_MEM);
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index 7dd8f29..ff56e87 100644
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
    /* This is not so much the SDRAM map as it is the whole localbus map. */
    SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
    SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index 2ec3ccc..758bd70 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
     * TLB 3:	256M	Non-cacheable, guarded
     * 0xc0000000	256M	Rapid IO MEM First half
     */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS,
    	      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
    	      0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
     * TLB 4:	256M	Non-cacheable, guarded
     * 0xd0000000	256M	Rapid IO MEM Second half
     */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000,
    	      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
    	      0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 545d869..17987e5 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -149,7 +149,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE,
+			       CONFIG_SYS_PCIE3_MEM_BUS,
    		       CONFIG_SYS_PCIE3_MEM_PHYS,
    		       CONFIG_SYS_PCIE3_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -161,10 +161,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCIE3_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE2,
+			       CONFIG_SYS_PCIE3_MEM_BUS2,
    		       CONFIG_SYS_PCIE3_MEM_PHYS2,
    		       CONFIG_SYS_PCIE3_MEM_SIZE2,
    		       PCI_REGION_MEM);
@@ -183,7 +183,7 @@ pci_init_board(void)
    	 * Activate ULI1575 legacy chip by performing a fake
    	 * memory access.  Needed to make ULI RTC work.
    	 */
-		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
+		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
    } else {
    	printf ("    PCIE3: disabled\n");
    }
@@ -216,7 +216,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
    		       CONFIG_SYS_PCIE1_MEM_PHYS,
    		       CONFIG_SYS_PCIE1_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -228,10 +228,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCIE1_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_BUS2,
    		       CONFIG_SYS_PCIE1_MEM_PHYS2,
    		       CONFIG_SYS_PCIE1_MEM_SIZE2,
    		       PCI_REGION_MEM);
@@ -279,7 +279,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE,
+			       CONFIG_SYS_PCIE2_MEM_BUS,
    		       CONFIG_SYS_PCIE2_MEM_PHYS,
    		       CONFIG_SYS_PCIE2_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -291,10 +291,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCIE2_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE2_MEM_BASE2,
+			       CONFIG_SYS_PCIE2_MEM_BUS2,
    		       CONFIG_SYS_PCIE2_MEM_PHYS2,
    		       CONFIG_SYS_PCIE2_MEM_SIZE2,
    		       PCI_REGION_MEM);
@@ -347,7 +347,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
    		       CONFIG_SYS_PCI1_MEM_PHYS,
    		       CONFIG_SYS_PCI1_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -359,10 +359,10 @@ pci_init_board(void)
    		       CONFIG_SYS_PCI1_IO_SIZE,
    		       PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
    	/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE3_MEM_BASE2,
+			       CONFIG_SYS_PCIE3_MEM_BUS2,
    		       CONFIG_SYS_PCIE3_MEM_PHYS2,
    		       CONFIG_SYS_PCIE3_MEM_SIZE2,
    		       PCI_REGION_MEM);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index af5ff42..1a1e659 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -329,7 +329,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
    		       CONFIG_SYS_PCI1_MEM_PHYS,
    		       CONFIG_SYS_PCI1_MEM_SIZE,
    		       PCI_REGION_MEM);
@@ -413,7 +413,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
    		       CONFIG_SYS_PCIE1_MEM_PHYS,
    		       CONFIG_SYS_PCIE1_MEM_SIZE,
    		       PCI_REGION_MEM);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index eab212a..e96c9a7 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
    /*
     * TLB 2:	256M	Non-cacheable, guarded
     */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS,
    	      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
    	      0, 2, BOOKE_PAGESZ_256M, 1),
/*
     * TLB 3:	256M	Non-cacheable, guarded
     */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000,
    	      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
    	      0, 3, BOOKE_PAGESZ_256M, 1),
 #endif
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index 7dd8f29..ff56e87 100644
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
    /* This is not so much the SDRAM map as it is the whole localbus map. */
    SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
    SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index 2ec3ccc..758bd70 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
     * TLB 3:	256M	Non-cacheable, guarded
     * 0xc0000000	256M	Rapid IO MEM First half
     */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS,
    	      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
    	      0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
     * TLB 4:	256M	Non-cacheable, guarded
     * 0xd0000000	256M	Rapid IO MEM Second half
     */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000,
    	      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
    	      0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index da7b6dc..a06ac2a 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -54,7 +54,7 @@ struct law_entry law_table[] = {
    SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
    SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
    SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_SRIO_MEM_BUS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
    /* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
    SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 688d8c3..996cb3a 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -409,7 +409,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-				CONFIG_SYS_PCI1_MEM_BASE,
+				CONFIG_SYS_PCI1_MEM_BUS,
    			CONFIG_SYS_PCI1_MEM_PHYS,
    			CONFIG_SYS_PCI1_MEM_SIZE,
    			PCI_REGION_MEM);
@@ -462,7 +462,7 @@ pci_init_board(void)
/* outbound memory */
    	pci_set_region(r++,
-				CONFIG_SYS_PCIE1_MEM_BASE,
+				CONFIG_SYS_PCIE1_MEM_BUS,
    			CONFIG_SYS_PCIE1_MEM_PHYS,
    			CONFIG_SYS_PCIE1_MEM_SIZE,
    			PCI_REGION_MEM);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 3e8052f..17c5eb3 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -197,7 +197,7 @@ void pci_init_board(void)
/* outbound memory */
    		pci_set_region(r++,
-					CONFIG_SYS_PCIE3_MEM_BASE,
+					CONFIG_SYS_PCIE3_MEM_BUS,
    				CONFIG_SYS_PCIE3_MEM_PHYS,
    				CONFIG_SYS_PCIE3_MEM_SIZE,
    				PCI_REGION_MEM);
@@ -264,7 +264,7 @@ void pci_init_board(void)
/* outbound memory */
    		pci_set_region(r++,
-					CONFIG_SYS_PCIE2_MEM_BASE,
+					CONFIG_SYS_PCIE2_MEM_BUS,
    				CONFIG_SYS_PCIE2_MEM_PHYS,
    				CONFIG_SYS_PCIE2_MEM_SIZE,
    				PCI_REGION_MEM);
@@ -317,7 +317,7 @@ void pci_init_board(void)
/* outbound memory */
    		pci_set_region(r++,
-					CONFIG_SYS_PCIE1_MEM_BASE,
+					CONFIG_SYS_PCIE1_MEM_BUS,
    				CONFIG_SYS_PCIE1_MEM_PHYS,
    				CONFIG_SYS_PCIE1_MEM_SIZE,
    				PCI_REGION_MEM);
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 112f18c..513c4fd 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -31,6 +31,14 @@
#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
+#ifndef CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
+#endif
+
 static struct pci_controller *pci_hose;
void
@@ -80,7 +88,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
    	pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
    }
-	pcix->potar1   = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pcix->potar1   = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
    pcix->potear1  = 0x00000000;
    pcix->powbar1  = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
    pcix->powbear1 = 0x00000000;
@@ -105,7 +113,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
    pcix->piwar3 = 0;
pci_set_region(hose->regions + 0,
-		       CONFIG_SYS_PCI1_MEM_BASE,
+		       CONFIG_SYS_PCI1_MEM_BUS,
    	       CONFIG_SYS_PCI1_MEM_PHYS,
    	       CONFIG_SYS_PCI1_MEM_SIZE,
    	       PCI_REGION_MEM);
@@ -165,7 +173,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
     */
    pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-	pcix2->potar1   = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
+	pcix2->potar1   = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
    pcix2->potear1  = 0x00000000;
    pcix2->powbar1  = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
    pcix2->powbear1 = 0x00000000;
@@ -190,7 +198,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
    pcix2->piwar3 = 0;
pci_set_region(hose->regions + 0,
-		       CONFIG_SYS_PCI2_MEM_BASE,
+		       CONFIG_SYS_PCI2_MEM_BUS,
    	       CONFIG_SYS_PCI2_MEM_PHYS,
    	       CONFIG_SYS_PCI2_MEM_SIZE,
    	       PCI_REGION_MEM);
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index acd6823..add8452 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -361,32 +361,32 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0x98000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 79a52d9..9948811 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -310,16 +310,16 @@
 #define CONFIG_SYS_I2C_OFFSET		0x3000
/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BUS
 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
/*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7ada8a2..9ac16e4 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -343,15 +343,15 @@ extern unsigned long get_clock_freq(void);
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
-#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index cdbbea6..d24d12b 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -269,38 +269,38 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
 #define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
 #define CONFIG_SYS_PCIE3_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_MEM_BASE2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2	CONFIG_SYS_PCIE3_MEM_BASE2
+#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2	CONFIG_SYS_PCIE3_MEM_BUS2
 #define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
#if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 083afba..2aeb8c3 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -369,16 +369,16 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	0xe2800000
@@ -386,8 +386,8 @@ extern unsigned long get_clock_freq(void);
 #endif
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
@@ -398,7 +398,7 @@ extern unsigned long get_clock_freq(void);
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
+#define CONFIG_SYS_RIO_MEM_BUS	0xC0000000
 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
 #endif
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index f9419cc..e500df4 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -341,15 +341,15 @@ extern unsigned long get_clock_freq(void);
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index f67d489..acd5454 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -302,16 +302,16 @@
 #define CONFIG_SYS_I2C_OFFSET		0x3000
/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BUS
 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
/*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ab3e6d6..07695c3 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -324,21 +324,21 @@ extern unsigned long get_clock_freq(void);
  * General PCI
  * Memory Addresses are mapped 1-1. I/O is mapped from 0
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
-#define CONFIG_SYS_SRIO_MEM_BASE	0xc0000000
+#define CONFIG_SYS_SRIO_MEM_BUS	0xc0000000
#ifdef CONFIG_QE
 /*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d604bd7..8596c2e 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -382,24 +382,24 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
-- 
1.5.6.5


    

[U-Boot] [PATCH 1/5] 85xx: Convert CONFIG_SYS_{PCI*, RIO*}_MEM_BASE to _MEM_BUS for FSL boards

Kumar Gala

[U-Boot] [PATCH 1/5] 85xx: Convert CONFIG_SYS_{PCI, RIO}_MEM_BASE to _MEM_BUS for FSL boards