Hi Dale,
On Monday 23 July 2007, Dale Dunlea wrote:
I have 2 AMCC yucca boards, one Rev A silicon, and one Rev B silicon.
Using commit 2721a68a9ea91f1e494649ce68b2577261f578e2, (8th March, 2007 "Small AMCC Katmai 440SPe update"), DDR2 works fine (with the original Micron DIMMS, anyway). But the next commit, 2f5df47351910a2936c7741cf111855829200943 (8th March, "Update AMCC Yucca 440SPe eval board support") which adds support for initialising SDRAM using the I2C prom, always reports:
"ERROR: Cannot determine a common read delay for the DIMM(s) installed."
This happens on both the Rev A board, and the Rev B board. Oddly enough, on our own custom board which is very similar to the Yucca, it passes fine.
Has anyone ever seen this before?
Not exactly as you described. It is know though, that Yucca Rev A boards were having problems with the current common SPD DDR2 memory detection code. But just recently I fixed this Rev A issue in the u-boot-ppc4xx repository:
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-ppc4xx.git;a=commit;h=...
So please download the current u-boot-ppc4xx repository and give it a try. And please let me know if it works on your Yucca's (Rev A and B) and your custom board.
Thanks.
Best regards, Stefan
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