
On 4/15/20 11:00 AM, Ley Foon Tan wrote: [...]
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h @@ -6,76 +6,65 @@
[...]
+/* FW DDR MPU F2S SCR */ +#define FW_DDR_MPU_F2S_SCR_EN 0x00 +#define FW_DDR_MPU_F2S_SCR_MPUR0 0x10 +#define FW_DDR_MPU_F2S_SCR_MPUR1 0x14 +#define FW_DDR_MPU_F2S_SCR_MPUR2 0x18 +#define FW_DDR_MPU_F2S_SCR_MPUR3 0x1c
These can be: #define FW_DDR_MPU_F2S_SCR_MPUR(n) (0x10 + (n) * 4)
and the other macros can be reduced in a similar manner.
+#define FW_DDR_MPU_F2S_SCR_F2S0_R0 0x20 +#define FW_DDR_MPU_F2S_SCR_F2S0_R1 0x24 +#define FW_DDR_MPU_F2S_SCR_F2S0_R2 0x28 +#define FW_DDR_MPU_F2S_SCR_F2S0_R3 0x2c +#define FW_DDR_MPU_F2S_SCR_F2S1_R0 0x30 +#define FW_DDR_MPU_F2S_SCR_F2S1_R1 0x34 +#define FW_DDR_MPU_F2S_SCR_F2S1_R2 0x38 +#define FW_DDR_MPU_F2S_SCR_F2S1_R3 0x3c +#define FW_DDR_MPU_F2S_SCR_F2S2_R0 0x40 +#define FW_DDR_MPU_F2S_SCR_F2S2_R1 0x44 +#define FW_DDR_MPU_F2S_SCR_F2S2_R2 0x48 +#define FW_DDR_MPU_F2S_SCR_F2S2_R3 0x4c
+/* FW DDR L3 DDR SCR */ +#define FW_DDR_L3_SCR_EN 0x00 +#define FW_DDR_L3_SCR_HPS_R0_ADDR 0x0c +#define FW_DDR_L3_SCR_HPS_R1_ADDR 0x10 +#define FW_DDR_L3_SCR_HPS_R2_ADDR 0x14 +#define FW_DDR_L3_SCR_HPS_R3_ADDR 0x18 +#define FW_DDR_L3_SCR_HPS_R4_ADDR 0x1c +#define FW_DDR_L3_SCR_HPS_R5_ADDR 0x20 +#define FW_DDR_L3_SCR_HPS_R6_ADDR 0x24 +#define FW_DDR_L3_SCR_HPS_R7_ADDR 0x28
[...]
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM) /* If the IOSSM/full FPGA is already loaded, start DDR */
- if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
ddr_calibration_sequence();
- if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) {
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
This should be printf(), since it's an error, no ?
hang();
}
- }
+#endif
if (!is_fpgamgr_user_mode()) fpgamgr_program(buf, FPGA_BUFSIZ, 0); diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 8f590dc5f611..30ee884dcf47 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -2,7 +2,7 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
- select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
- select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
- select RAM
- select SPL_RAM
Shouldn't this be selected for Arria 10 only ?
[...]