On Wed, Aug 20, 2014 at 12:24:11PM -0600, Stephen Warren wrote:
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding treding@nvidia.com
Implement the powergate API that allows various power partitions to be power up and down.
diff --git a/arch/arm/cpu/tegra-common/powergate.c b/arch/arm/cpu/tegra-common/powergate.c
+static int tegra_powergate_set(enum tegra_powergate id, bool state)
- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
Since the power-down/up is an asynchronous operation, don't you need to wait for it to complete here?
It seems like the PWRGATE_STATUS register can be polled to determine when the operation is finished. I'll implement a loop with a small timeout here. We probably need to do the same in the kernel.
Apparently for newer SoCs (starting with Tegra114) the meaning of the PWRGATE_TOGGLE_START bit has also changed. It should be polled until cleared before starting a new operation and once an operation has been started (PWRGATE_TOGGLE_START set) the bit should be polled until it is cleared again to check that the request was accepted by the PMC.
- return 0;
+}
+static int tegra_powergate_remove_clamping(enum tegra_powergate id) +{
- unsigned long value;
- if (id == TEGRA_POWERGATE_VDEC)
value = 1 << TEGRA_POWERGATE_PCIE;- else if (id == TEGRA_POWERGATE_PCIE)
value = 1 << TEGRA_POWERGATE_VDEC;- else
value = 1 << id;A comment indicating why there's a special case here would be useful.
Isn't the special-case (HW design bug) restricted to Tegra20, or did it carry over into later chips in order to maintain HW register compatibility?
As far as I can tell this was carried over for register compatibility. The bits for the PCIE and VDEC partitions are still reversed in Tegra124.
diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h
+enum tegra_powergate {
- TEGRA_POWERGATE_CPU,
- TEGRA_POWERGATE_3D,
- TEGRA_POWERGATE_VENC,
- TEGRA_POWERGATE_PCIE,
- TEGRA_POWERGATE_VDEC,
- TEGRA_POWERGATE_L2,
- TEGRA_POWERGATE_MPE,
- TEGRA_POWERGATE_HEG,
- TEGRA_POWERGATE_SATA,
- TEGRA_POWERGATE_CPU1,
- TEGRA_POWERGATE_CPU2,
- TEGRA_POWERGATE_CPU3,
- TEGRA_POWERGATE_CELP,
- TEGRA_POWERGATE_3D1,
+};
I thought the list of partitions varied a bit by chip?
The list of valid partitions varies per chip, but the list of values remains compatible. For the same reason we have a list of partitions in the Linux kernel, but they are checked for validity against the per-SoC list. Not sure if we need to go that far with U-Boot.
Thierry