This is required for better performance, and performs below tuning: 1. Enable burst length set, and define it as 4/8/16. 2. Set burst request limit to 16 requests.
Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Sriram Dash sriram.dash@nxp.com --- Changes in v2: - using clrsetbits_le32 and setbits_le32 instead of writel
drivers/usb/host/xhci-fsl.c | 10 ++++++++++ include/linux/usb/xhci-fsl.h | 3 +++ 2 files changed, 13 insertions(+)
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index bdcd4f1..0e3e056 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -58,6 +58,13 @@ static void fsl_apply_xhci_errata(void) } }
+static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg) +{ + clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK, + USB3_ENABLE_BEAT_BURST); + setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT); +} + static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) { int ret = 0; @@ -74,6 +81,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */ dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+ /* Change beat burst and outstanding pipelined transfers requests */ + fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg); + return ret; }
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 199f366..1032763 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -20,6 +20,9 @@ #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) #define USB3_PWRCTL_CLK_CMD_SHIFT 14 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 +#define USB3_ENABLE_BEAT_BURST 0xF +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF +#define USB3_SET_BEAT_BURST_LIMIT 0xF00
/* USBOTGSS_WRAPPER definitions */ #define USBOTGSS_WRAPRESET BIT(17)