Now we need to specify flags for each GDSC for it to function properly. Copy .flags field from respective Linux GCC driver.
Turns out, even among SDM845 not all GDSCs are the same. Some of GDSCs do specify the POLL_CFG_GDSCR flag that changes the logic to check the ON/OFF status, other don't.
Some qcom clock drivers in U-Boot don't specify any GDSCs at all (apq8016, apq8096, ipq4019, qcs404), or GDSCs in their linux GCC driver don't specify any flags (qcm2290, sm6115) thus making them unaffected by this change.
Add flags to all other SoC's GDSCs currently present in U-Boot that do need this change.
Signed-off-by: Alexey Minnekhanov alexeymin@postmarketos.org --- drivers/clk/qcom/clock-sc7280.c | 4 ++-- drivers/clk/qcom/clock-sdm845.c | 26 +++++++++++++------------- drivers/clk/qcom/clock-sm8150.c | 14 +++++++------- drivers/clk/qcom/clock-sm8550.c | 16 ++++++++-------- drivers/clk/qcom/clock-sm8650.c | 16 ++++++++-------- 5 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 5d343f120519..cacad0eda164 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -98,8 +98,8 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = { };
static const struct qcom_power_map sc7280_gdscs[] = { - [GCC_UFS_PHY_GDSC] = { 0x77004 }, - [GCC_USB30_PRIM_GDSC] = { 0xf004 }, + [GCC_UFS_PHY_GDSC] = { 0x77004, .flags = VOTABLE }, + [GCC_USB30_PRIM_GDSC] = { 0xf004, .flags = VOTABLE }, };
static struct msm_clk_data qcs404_gcc_data = { diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index adffb0cb2402..53068bd3baa4 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -188,19 +188,19 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { };
static const struct qcom_power_map sdm845_gdscs[] = { - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [UFS_CARD_GDSC] = { 0x75004 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [USB30_PRIM_GDSC] = { 0xf004 }, - [USB30_SEC_GDSC] = { 0x10004 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, - [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, + [PCIE_0_GDSC] = { 0x6b004, .flags = POLL_CFG_GDSCR }, + [PCIE_1_GDSC] = { 0x8d004, .flags = POLL_CFG_GDSCR }, + [UFS_CARD_GDSC] = { 0x75004, .flags = POLL_CFG_GDSCR }, + [UFS_PHY_GDSC] = { 0x77004, .flags = POLL_CFG_GDSCR }, + [USB30_PRIM_GDSC] = { 0xf004, .flags = POLL_CFG_GDSCR }, + [USB30_SEC_GDSC] = { 0x10004, .flags = POLL_CFG_GDSCR }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044, .flags = VOTABLE }, };
static const phys_addr_t sdm845_gpll_addrs[] = { diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c index 88f2e678f43c..3bff73de0481 100644 --- a/drivers/clk/qcom/clock-sm8150.c +++ b/drivers/clk/qcom/clock-sm8150.c @@ -281,13 +281,13 @@ static const struct qcom_reset_map sm8150_gcc_resets[] = { };
static const struct qcom_power_map sm8150_gcc_power_domains[] = { - [EMAC_GDSC] = { 0x6004 }, - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [UFS_CARD_GDSC] = { 0x75004 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [USB30_PRIM_GDSC] = { 0xf004 }, - [USB30_SEC_GDSC] = { 0x10004 }, + [EMAC_GDSC] = { 0x6004, .flags = POLL_CFG_GDSCR }, + [PCIE_0_GDSC] = { 0x6b004, .flags = POLL_CFG_GDSCR }, + [PCIE_1_GDSC] = { 0x8d004, .flags = POLL_CFG_GDSCR }, + [UFS_CARD_GDSC] = { 0x75004, .flags = POLL_CFG_GDSCR }, + [UFS_PHY_GDSC] = { 0x77004, .flags = POLL_CFG_GDSCR }, + [USB30_PRIM_GDSC] = { 0xf004, .flags = POLL_CFG_GDSCR }, + [USB30_SEC_GDSC] = { 0x10004, .flags = POLL_CFG_GDSCR }, };
static struct msm_clk_data sm8150_clk_data = { diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index c0249925cc7e..d8368688afaa 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -229,14 +229,14 @@ static const struct qcom_reset_map sm8550_gcc_resets[] = { };
static const struct qcom_power_map sm8550_gdscs[] = { - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_0_PHY_GDSC] = { 0x6c000 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [PCIE_1_PHY_GDSC] = { 0x8e000 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [UFS_MEM_PHY_GDSC] = { 0x9e000 }, - [USB30_PRIM_GDSC] = { 0x39004 }, - [USB3_PHY_GDSC] = { 0x50018 }, + [PCIE_0_GDSC] = { 0x6b004, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [PCIE_0_PHY_GDSC] = { 0x6c000, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [PCIE_1_GDSC] = { 0x8d004, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [PCIE_1_PHY_GDSC] = { 0x8e000, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_PHY_GDSC] = { 0x77004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_MEM_PHY_GDSC] = { 0x9e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB30_PRIM_GDSC] = { 0x39004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB3_PHY_GDSC] = { 0x50018, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, };
static struct msm_clk_data sm8550_gcc_data = { diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 0ce83e9b2437..e5b8e6a10be3 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -226,14 +226,14 @@ static const struct qcom_reset_map sm8650_gcc_resets[] = { };
static const struct qcom_power_map sm8650_gdscs[] = { - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_0_PHY_GDSC] = { 0x6c000 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [PCIE_1_PHY_GDSC] = { 0x8e000 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [UFS_MEM_PHY_GDSC] = { 0x9e000 }, - [USB30_PRIM_GDSC] = { 0x39004 }, - [USB3_PHY_GDSC] = { 0x50018 }, + [PCIE_0_GDSC] = { 0x6b004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [PCIE_0_PHY_GDSC] = { 0x6c000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [PCIE_1_GDSC] = { 0x8d004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [PCIE_1_PHY_GDSC] = { 0x8e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [UFS_PHY_GDSC] = { 0x77004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_MEM_PHY_GDSC] = { 0x9e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB30_PRIM_GDSC] = { 0x39004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB3_PHY_GDSC] = { 0x50018, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, };
static struct msm_clk_data sm8650_gcc_data = {