Hi Dave, It still shows data tlb error tho. I found it occur error around the GET_GOT of start.s. The SRR0 and SRR1 show the error address of system.map is _start_cont. Suspect the DDR setting problem ?? But I thought all the DDR setting are from SPD. So, I didn't set any entry of DDR in TLB1. Any hint?
Liu Dave-R63238 wrote:
EELADR - 0XF4010000, it is INIT_RAM address, why the
transaction with
address(0xF4010000) go to system bus? It should keep in the cache due to cache lock, never out to
system bus.
I don't know why... and it just happened.... shall I allocate a entry of tlb for it?? or cover it in some space ?
Not need.
A quick question is, there is a FPGA(actel pixis) in mpc8544ds board, and it seems related with system clock ??? There is no such FPGA in my board, is it the problem??
It is possible to be problem.
Shall I remove the pixis related code from board.h and board.c and try to configure system clock by myself ?? Still confusing.....
Yes, remove the pixis related code. Configure the sys clk directly.
Thanks, Dave _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot