Enable CPLD_Dn pull down resistor instead of pull up to avoid intefering with CPLD power off functionality.
Signed-off-by: Marek Vasut marex@denx.de --- Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Fabio Estevam festevam@gmail.com Cc: Francesco Dolcini francesco.dolcini@toradex.com Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Cc: Philippe Schenker philippe.schenker@toradex.com Cc: Martyn Welch martyn.welch@collabora.com Cc: Stefano Babic sbabic@denx.de Cc: u-boot@lists.denx.de --- arch/arm/dts/imx8mm-mx8menlo.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts index 0b123a84018..c226285c6ea 100644 --- a/arch/arm/dts/imx8mm-mx8menlo.dts +++ b/arch/arm/dts/imx8mm-mx8menlo.dts @@ -290,6 +290,28 @@ >; };
+&pinctrl_gpio_hog1 { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* CPLD_int */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* CPLD_reset */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184 /* CPLD_D[7] */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184 /* CPLD_D[6] */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184 /* CPLD_D[5] */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184 /* CPLD_D[4] */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184 /* CPLD_D[3] */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184 /* CPLD_D[2] */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184 /* CPLD_D[1] */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184 /* CPLD_D[0] */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4 /* KBD_intK */ + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4 /* DISP_reset */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4 /* KBD_intI */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4 + >; +}; + ®_usb_otg1_vbus { /delete-property/ enable-active-high; gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;