At present SPL is used on 64-bit platforms, to allow SPL to be built as a 32-bit program and U-Boot proper to be built as 64-bit.
However it is useful to be able to use SPL on any x86 platform, where U-Boot needs to be updated in the field. Then SPL can select which U-Boot to run (A or B) and most of the code can be updated. Similarly, using TPL allows both SPL and U-Boot to be updated. This is the best approach, since it means that all of U-Boot proper as well as SPL (in particular SDRAM init) can be updated in the field. This provides for the smallest possible amount of read-only (non-updateable) code: just the TPL code.
This series contains a number of changes to allow x86 boards to use TPL, SPL and U-Boot proper. As a test, it is enabled for samus with a new chromebook_samus_tpl board.
Changes in v3: - Rebase to x86/master - Use acpi_s3.h header for constants (and tidy up header order) - Fix multi-line comment format - Remove unneeded pch-reset node - Drop unnecessary change to chromebook_link_defconfig
Changes in v2: - Update the commit message to explain the implications on aliases - Add new patch to separate out the EFI code in sysreset - Add new patch to implement power-off if available - Add a comment about the hard-coded text base - Add new patch to enable the RTC in Kconfig - Add a new patch to update PCH to work in TPL - Add a new patch allowing jumping from TPL to SPL - Sort defconfig and adjust it to build after rebase on maste
Simon Glass (18): cros_ec: Use a hyphen in the uclass name x86: Add a simple TPL implementation x86: sysreset: Separate out the EFI code x86: sysreset: Implement power-off if available x86: sysreset: Implement the get_last() method x86: Add documention on the samus flashmap x86: samus: Update device tree for SPL x86: samus: Update device tree for verified boot x86: Update device tree for TPL x86: Update device tree for Chromium OS verified boot x86: Fix device-tree indentation x86: samus: Increase the pre-reloc memory again Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" x86: Enable the RTC on all boards x86: Update the memory map a little x86: broadwell: Update PCH to work in TPL x86: Add a way to jump from TPL to SPL x86: samus: Add a target to boot through TPL
arch/Kconfig | 1 + arch/x86/cpu/broadwell/pch.c | 12 +- arch/x86/cpu/start.S | 13 ++ arch/x86/dts/chromebook_samus.dts | 55 +++++++- arch/x86/dts/u-boot.dtsi | 162 ++++++++++++++-------- arch/x86/include/asm/spl.h | 17 ++- arch/x86/lib/Makefile | 9 +- arch/x86/lib/spl.c | 44 +++++- arch/x86/lib/tpl.c | 118 ++++++++++++++++ board/google/Kconfig | 8 ++ board/google/chromebook_samus/Kconfig | 14 +- board/google/chromebook_samus/MAINTAINERS | 7 + configs/chromebook_samus_defconfig | 2 +- configs/chromebook_samus_tpl_defconfig | 82 +++++++++++ doc/README.x86 | 16 +++ drivers/misc/cros_ec.c | 2 +- drivers/sysreset/sysreset_x86.c | 101 +++++++++++++- include/configs/chromebook_link.h | 3 - include/configs/chromebook_samus.h | 2 + include/configs/qemu-x86.h | 5 - include/configs/x86-common.h | 1 - include/pci.h | 6 +- 22 files changed, 583 insertions(+), 97 deletions(-) create mode 100644 arch/x86/lib/tpl.c create mode 100644 configs/chromebook_samus_tpl_defconfig