This set of patches updates the interface to the DDR calibration in preparation for the addition of a pseudo-board for calibration on i.MX6.
The first patch fixes an ommission in the use of the DG_CMP_CYC flag in register MPDGCTRL0.
The second patch cleans up the handling of bus widths by passing the system configuration information to the calibration routines.
The third routine adds support for returning the calibration data written to the MMDC registers.
Eric Nelson (3): mx6: ddr: allow 32 cycles for DQS gating calibration mx6: ddr: pass mx6_ddr_sysinfo to calibration routines mx6: ddr: add mmdc_read_calibration routine to return dynamic data
arch/arm/cpu/armv7/mx6/ddr.c | 128 +++++++++++++++++++++----------- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 6 +- board/kosagi/novena/novena_spl.c | 4 +- 3 files changed, 92 insertions(+), 46 deletions(-)