On 27.07.22 14:47, Pali Rohár wrote:
- Replace skeleton.dtsi by explicit #address-cells / #size-cells
- Add sdramc@1400 and phy@18300 nodes
- Remove (unused) timeout-ms i2c properties
- Fix compatible string for UARTs
- Add interrupts properties for watchdog
Signed-off-by: Pali Rohár pali@kernel.org
Applied to u-boot-marvell/master
Thanks, Stefan
arch/arm/dts/armada-38x.dtsi | 55 ++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 6979c0c50584..7731a205698e 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -9,13 +9,15 @@
- Thomas Petazzoni thomas.petazzoni@free-electrons.com
*/
-#include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "Marvell Armada 38x family SoC"; compatible = "marvell,armada380";
@@ -103,6 +105,11 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
sdramc: sdramc@1400 {compatible = "marvell,armada-xp-sdram-controller";reg = <0x1400 0x500>;};L2: cache-controller@8000 { compatible = "arm,pl310-cache"; reg = <0x8000 0x1000>;@@ -148,7 +155,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; };@@ -159,13 +165,12 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; uart0: serial@12000 {compatible = "snps,dw-apb-uart";
compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;@@ -175,7 +180,7 @@ };
uart1: serial@12100 {
compatible = "snps,dw-apb-uart";
compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;@@ -338,6 +343,44 @@ #clock-cells = <1>; };
comphy: phy@18300 {compatible = "marvell,armada-380-comphy";reg-names = "comphy", "conf";reg = <0x18300 0x100>, <0x18460 4>;#address-cells = <1>;#size-cells = <0>;comphy0: phy@0 {reg = <0>;#phy-cells = <1>;};comphy1: phy@1 {reg = <1>;#phy-cells = <1>;};comphy2: phy@2 {reg = <2>;#phy-cells = <1>;};comphy3: phy@3 {reg = <3>;#phy-cells = <1>;};comphy4: phy@4 {reg = <4>;#phy-cells = <1>;};comphy5: phy@5 {reg = <5>;#phy-cells = <1>;};};coreclk: mvebu-sar@18600 { compatible = "marvell,armada-380-core-clock"; reg = <0x18600 0x04>;@@ -379,6 +422,8 @@ reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed";
interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; }; cpurst: cpurst@20800 {
Viele Grüße, Stefan Roese