Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Changes for v2: Updated Makefile Changes for v3: - Updated B4860QDS.h config file to support B4420QDS NAND boot - Fix B4860QDS_SPIFLASH B4420QDS_SPIFLASH build issue
Add support of 2 stage NAND boot loader in cornet platforms using SPL framework.
In current secenrio size of u-boot can become >=512KB. So This patch set will be helpful for those SoC which has less internal SRAM(512KB).
here, PBL initialise the internal SRAM and copy SPL(192K) in SRAM. SPL further initialise DDR using SPD and environment variables and copy u-boot(768 KB) from flash to DDR. Finally SPL transer control to u-boot for futher booting.
SPL has following features: - Executes within 256K - No relocation required
Run time view of SPL framework :- ----------------------------------------------- Area | Address | ----------------------------------------------- GD, BD | 0xFFFC0000 | ----------------------------------------------- ENV | 0xFFFC1000 | ----------------------------------------------- HEAP | 0xFFFC2800 | ----------------------------------------------- STACK | 0xFFFD0000 | ----------------------------------------------- U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) | -----------------------------------------------
NAND Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size 0x000000 0x0FFFFF u-boot 1MB 0x140000 0x15FFFF u-boot env 128KB 0x160000 0x17FFFF FMAN Ucode 128KB --- This patch set contains:-
[PATCH 1/7] powerpc/mpc85xx: Move LAW_EN define outside of config
[PATCH 2/7] powerpc/mpc85xx: Avoid hardcoding in SPL linker script
[PATCH 3/7] powerpc:Add support of SPL non-relocation
[PATCH 4/7] powerpc/mpc8xxx:Allow Parsing of LAW table in both SPL & non SPL
[PATCH 5/7] driver/ifc: define nand_spl_load_image() for SPL
[PATCH 6/7] Makefile: Add support of RAMBOOT_SPLPBL
[PATCH 7/7] B4860QDS: Add support of 2 stage NAND boot loader