Cache configuration methods is different for LPAE and non-LPAE cases. Hence the bits and the interpretaion is different for two cases. In case of non-LPAE mode short descriptor format is used and we need to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0 lookup.
Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/cpu/armv7/omap-common/omap-cache.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c index ee89f1f..b37163a 100644 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -17,7 +17,28 @@
DECLARE_GLOBAL_DATA_PTR;
-#define ARMV7_DCACHE_WRITEBACK 0xe +/* + * Without LPAE short descriptors are used + * Set C - Cache Bit3 + * Set B - Buffer Bit2 + * The last 2 bits set to 0b10 + * Do Not set XN bit4 + * So value is 0xe + * + * With LPAE cache configuration happens via MAIR0 register + * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. + * 0xFF maps to Cache writeback with Read and Write Allocate set + * The bits[1:0] should have the value 0b01 for the first level + * descriptor. + * So the value is 0xd + */ + +#ifdef CONFIG_ARMV7_LPAE +#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC +#else +#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK +#endif + #define ARMV7_DOMAIN_CLIENT 1 #define ARMV7_DOMAIN_MASK (0x3 << 0)
@@ -38,7 +59,7 @@ void dram_bank_mmu_setup(int bank)
debug("%s: bank: %d\n", __func__, bank); for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + set_section_dcache(i, ARMV7_DCACHE_POLICY); }
void arm_init_domains(void)