1. We have
an AMCC Yucca board using a processor with PVR 53421890 (revA
silicon), the start.s code runs fine.
2. When running this
same code on our board with PVR version 53421891 (revB silicon) we always have
an ESR set to 0x8000000, as soon as we enable the MSR[ME] Bit is set we of
course get a machine check.
3. We have tried a Denx patch to write all
three words of the TLB table (to make sure no parity errors are occuring)
however we still have the problem.
4. We have applied a Denx patch to write the
TLB table depending on whether its revA or revB silicon.
Neither patch has cured the
problem?
Has anybody seen this issue ?
William
Oppermann