Re: [U-Boot] [PATCH v5 2/3] wandboard: add Future Eletronics 7" WVGA LCD extension board

6 Jan 2014

      On Mon, Jan 6, 2014 at 1:27 PM, Otavio Salvador otavio@ossystems.com.br wrote:
[Removed wandboard -devel list as it bounces when I reply to it]
...
-int board_video_skip(void)
-{

  int ret;

+static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {

  MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,

  MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */

  MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */

  MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04

          | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */

  MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */

  MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,

  MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,

  MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,

  MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,

  MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,

  MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,

  MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,

  MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,

  MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,

  MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,

  MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,

  MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,

  MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,

  MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,

  MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,

  MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,

  MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,

  MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,

  MX6_PAD_SD4_DAT2__GPIO2_IO10

          | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */

  MX6_PAD_SD4_DAT3__GPIO2_IO11

          | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */

+};
Here you enable the parallel data lines for the display ....
...
static void setup_display(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

  struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  int reg;

  enable_ipu_clock();
  imx_setup_hdmi();

  /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */

  reg = __raw_readl(&mxc_ccm->CCGR3);

  reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;

  writel(reg, &mxc_ccm->CCGR3);

  /* set LDB0, LDB1 clk select to 011/011 */

  reg = readl(&mxc_ccm->cs2cdr);

  reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK

           | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);

  reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)

        | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);

  writel(reg, &mxc_ccm->cs2cdr);

,but here you enable the LDB clocks.
Why do you need to enable the LDB clocks for driving the parallel display?
Regards,
Fabio Estevam