CS4315 PHY doesn't support phy-reset by software, it needs to reset it by hardware via CPLD control.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- board/freescale/t208xrdb/cpld.h | 3 +++ board/freescale/t208xrdb/t208xrdb.c | 7 +++++++ 2 files changed, 10 insertions(+)
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index 3f15338..9bd5247 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 + +/* RSTCON Register */ +#define CPLD_RSTCON_EDC_RST 0x04 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index ad393df..0c2c1c5 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
int misc_init_r(void) { + u8 reg; + + /* Reset CS4315 PHY */ + reg = CPLD_READ(reset_ctl); + reg |= CPLD_RSTCON_EDC_RST; + CPLD_WRITE(reset_ctl, reg); + return 0; }