Hi,
On 30/08/2024 16:55, Chris Morgan wrote:
From: Chris Morgan macromorgan@hotmail.com
Correct the default TPR6 parameter based on suggestion from Mikhail Kalashnikov. [1]
[1] https://lore.kernel.org/u-boot/4c003cab-c8b8-484d-924d-084e71fe666e@gmail.co...
I am confused, doesn't that change belong together with the one that masks bits[23:16] instead bits[15:8]? So that the same 0xc0 end up in that register? Mikhail, can you confirm what the intention of your reply mentioned above was? To say that the vendor code masks the different set of bits, and to stay correct we also have to adjust the TPR6 default value? For OPi Zero2W and OPi Zero3 those two bytes are the same, but for the Tanix TX1 and the default value they are not.
Cheers, Andre
Fixes: 4b02f0120a4b ("sunxi: H616: add LPDDR4 DRAM support") Suggested-by: Mikhail Kalashnikov iuncuim@gmail.com Signed-off-by: Chris Morgan macromorgan@hotmail.com
arch/arm/mach-sunxi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 078f8c19fa..5b3571025f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -87,7 +87,7 @@ config DRAM_SUN50I_H616_TPR2
config DRAM_SUN50I_H616_TPR6 hex "H616 DRAM TPR6 parameter"
- default 0x3300c080
- default 0x33c00080 help TPR6 value from vendor DRAM settings.