Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Update NAND binding to add "nvidia," prefix
Changes in v3: - Add reg property for unit address (should be used for chip select) - Change note in fdt binding about the need for a hardware-specific binding - Fix up typos in fdt binding, and rename the file - Update fdt binding to make everything Nvidia-specific
arch/arm/dts/tegra20.dtsi | 6 ++ .../nand/nvidia,tegra20-nand.txt | 68 ++++++++++++++++++++ 2 files changed, 74 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index bc64f42..018a3c8 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -200,4 +200,10 @@ reg = <0x7000f400 0x200>; };
+ nand: nand-controller@70008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + }; }; diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file mode 100644 index 0000000..2484556 --- /dev/null +++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt @@ -0,0 +1,68 @@ +NAND Flash +---------- + +(there isn't yet a generic binding in Linux, so this describes what is in +U-Boot. There should not be Linux-specific or U-Boot specific binding, just +a binding that describes this hardware. But agreeing a binding in Linux in +the absence of a driver may be beyond my powers.) + +The device node for a NAND flash device is as follows: + +Required properties : + - compatible : Should be "manufacturer,device", "nand-flash" + - nvidia,page-data-bytes : Number of bytes in the data area + - nvidia,page-spare-bytes : Number of bytes in spare area + spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes + + tag-ecc-bytes + - nvidia,skipped-spare-bytes : Number of bytes to skip at start of spare area + (these are typically used for bad block maintenance) + - nvidia,data-ecc-bytes : Number of ECC bytes for data area + - nvidia,tag-bytes :Number of tag bytes in spare area + - nvidia,tag-ecc-bytes : Number ECC bytes to be generated for tag bytes + +This node should sit inside its controller. + + +Nvidia NAND Controller +---------------------- + +The device node for a NAND flash controller is as follows: + +Optional properties: + +nvidia,wp-gpios : GPIO of write-protect line, three cells in the format: + phandle, parameter, flags +nvidia,nand-width : bus width of the NAND device in bits + + - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns. + Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH), + TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL + + MAX_TRP_TREA is: + non-EDO mode: Max(tRP, tREA) + 6ns + EDO mode: tRP timing + +The 'reg' property should provide the chip select used by the flash chip. + + +Example +------- + +nand-controller@0x70008000 { + compatible = "nvidia,tegra20-nand"; + #address-cells = <1>; + #size-cells = <0>; + nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ + nvidia,nand-width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + nvidia,page-data-bytes = <2048>; + nvidia,tag-ecc-bytes = <4>; + nvidia,tag-bytes = <20>; + nvidia,data-ecc-bytes = <36>; + nvidia,skipped-spare-bytes = <4>; + nvidia,page-spare-bytes = <64>; + }; +};