This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only.
Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com ---
Changes in v1: - Added (better) help to KConfig - Added dt binding documentation - Fixed include ordering - Reworked msm_serial_getc - Added error handling to msm_uart_clk_init (that is ignored later for now) - Dropped unneeded DM_FLAG_PRE_RELOC
doc/device-tree-bindings/serial/msm-serial.txt | 6 + drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_msm.c | 206 +++++++++++++++++++++++++ 4 files changed, 221 insertions(+) create mode 100644 doc/device-tree-bindings/serial/msm-serial.txt create mode 100644 drivers/serial/serial_msm.c
diff --git a/doc/device-tree-bindings/serial/msm-serial.txt b/doc/device-tree-bindings/serial/msm-serial.txt new file mode 100644 index 0000000..48b8428 --- /dev/null +++ b/doc/device-tree-bindings/serial/msm-serial.txt @@ -0,0 +1,6 @@ +Qualcomm UART (Data Mover mode) + +Required properties: +- compatible: must be "qcom,msm-uartdm-v1.4" +- reg: start address and size of the registers +- clock: interface clock (must accept baudrate as a frequency) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..56d7b76 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -223,4 +223,12 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N.
+config MSM_SERIAL + bool "Qualcomm on-chip UART" + depends on DM_SERIAL + help + Support Data Mover UART used on Qualcomm Snapdragon SoCs. + It should support all Qualcomm devices with UARTDM version 1.4, + for example APQ8016 and MSM8916. + Single baudrate is supported in current implementation (115200). endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..d052175 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c new file mode 100644 index 0000000..344f254 --- /dev/null +++ b/drivers/serial/serial_msm.c @@ -0,0 +1,206 @@ +/* + * Qualcomm UART driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * UART will work in Data Mover mode. + * Based on Linux driver. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <serial.h> +#include <watchdog.h> +#include <asm/io.h> +#include <linux/compiler.h> + +/* Serial registers - this driver works in uartdm mode*/ + +#define UARTDM_DMRX 0x34 /* Max RX transfer length */ +#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ + +#define UARTDM_RXFS 0x50 /* RX channel status register */ +#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ +#define UARTDM_RXFS_BUF_MASK 0x7 + +#define UARTDM_SR 0xA4 /* Status register */ +#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ +#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */ +#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */ + +#define UARTDM_CR 0xA8 /* Command register */ +#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */ +#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */ +#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/ +#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */ +#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */ + +#define UARTDM_IMR 0xB0 /* Interrupt mask register */ +#define UARTDM_ISR 0xB4 /* Interrupt status register */ +#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */ + +#define UARTDM_TF 0x100 /* UART Transmit FIFO register */ +#define UARTDM_RF 0x140 /* UART Receive FIFO register */ + + +DECLARE_GLOBAL_DATA_PTR; + +struct msm_serial_data { + phys_addr_t base; + unsigned chars_cnt; /* number of buffered chars */ + uint32_t chars_buf; /* buffered chars */ +}; + +static int msm_serial_getc(struct udevice *dev) +{ + struct msm_serial_data *p = dev_get_priv(dev); + char c; + unsigned sr; + + if (!p->chars_buf) { + /* Clear error in case of buffer overrun */ + if (readl(p->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) + writel(UARTDM_CR_CMD_RESET_ERR, p->base + UARTDM_CR); + + /* We need to fetch new character */ + sr = readl(p->base + UARTDM_SR); + + if (sr & UARTDM_SR_RX_READY) { + /* There are at least 4 bytes in fifo */ + p->chars_buf = readl(p->base + UARTDM_RF); + p->chars_cnt = 4; + } else { + /* Check if there is anything in fifo */ + p->chars_cnt = readl(p->base + UARTDM_RXFS); + /* Extract number of characters in UART packing buffer*/ + p->chars_cnt = (p->chars_cnt >> UARTDM_RXFS_BUF_SHIFT) & + UARTDM_RXFS_BUF_MASK; + if (!p->chars_cnt) + return -EAGAIN; + + /* There is at least one charcter, move it to fifo */ + writel(UARTDM_CR_CMD_FORCE_STALE, p->base + UARTDM_CR); + + p->chars_buf = readl(p->base + UARTDM_RF); + writel(UARTDM_CR_CMD_RESET_STALE_INT, + p->base + UARTDM_CR); + writel(0xFFFFFF, p->base + UARTDM_DMRX); + } + } + + c = p->chars_buf & 0xFF; + p->chars_buf >>= 8; + p->chars_cnt--; + + return c; +} + +static int msm_serial_putc(struct udevice *dev, const char ch) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + if (!(readl(p->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) && + !(readl(p->base + UARTDM_ISR) & UARTDM_ISR_TX_READY)) + return -EAGAIN; + + writel(UARTDM_CR_CMD_RESET_TX_READY, p->base + UARTDM_CR); + + writel(1, p->base + UARTDM_NCF_TX); + writel(ch, p->base + UARTDM_TF); + return 0; +} + +static int msm_serial_pending(struct udevice *dev, bool input) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + if (input) { + if (p->chars_cnt) + return 1; + if (readl(p->base + UARTDM_SR) & UARTDM_SR_RX_READY) + return 1; + if (readl(p->base + UARTDM_RXFS)) + return 1; + } + return 0; +} + +static const struct dm_serial_ops msm_serial_ops = { + .putc = msm_serial_putc, + .pending = msm_serial_pending, + .getc = msm_serial_getc, +}; + +static int msm_uart_clk_init(struct udevice *dev) +{ + uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "clock-frequency", 115200); + uint clkd[2]; /* clk_id and clk_no */ + int clk_offset; + struct udevice *clk; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, + 2); + if (ret) + return ret; + + clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); + if (clk_offset < 0) + return clk_offset; + + ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk); + if (ret) + return ret; + + ret = clk_set_periph_rate(clk, clkd[1], clk_rate); + if (ret < 0) + return ret; + + return 0; +} + +static int msm_serial_probe(struct udevice *dev) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + msm_uart_clk_init(dev); /* Ignore return value and hope clock was + properly initialized by earlier loaders */ + + if (readl(p->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) + writel(UARTDM_CR_CMD_RESET_ERR, p->base + UARTDM_CR); + + writel(0, p->base + UARTDM_IMR); + writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, p->base + UARTDM_CR); + writel(0xFFFFFF, p->base + UARTDM_DMRX); + return 0; +} + +static int msm_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_serial_data *p = dev_get_priv(dev); + + p->base = dev_get_addr(dev); + if (p->base == FDT_ADDR_T_NONE) + return -EINVAL; + return 0; +} + +static const struct udevice_id msm_serial_ids[] = { + { .compatible = "qcom,msm-uartdm-v1.4" }, + { } +}; + +U_BOOT_DRIVER(serial_msm) = { + .name = "serial_msm", + .id = UCLASS_SERIAL, + .of_match = msm_serial_ids, + .ofdata_to_platdata = msm_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct msm_serial_data), + .probe = msm_serial_probe, + .ops = &msm_serial_ops, +};