Hi,
I did a little bit more work with git bisect and found an issue on commit c788ecfdc3eb577757ffc1bfb8416added07ef33 "nand: Move the sub-page read support enable to a flag".
Making this change on top of v2013.07 allowed me to again write to NAND correctly.
-#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) +#define NAND_HAS_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ + && (chip->page_shift > 9))
Like some other OMAP3 platforms, my platform uses 1-bit hardware ECC for the first NAND partition and software ECC elsewhere. Does this ecc.mode switch need to be partition specific?
--Ash
On Wed, Sep 4, 2013 at 11:00 AM, Ash Charles ashcharles@gmail.com wrote:
On Wed, Sep 4, 2013 at 1:54 AM, Andreas Bießmann andreas.devel@googlemail.com wrote:
I can't confirm your complaints. Here it works (at least on tricorder, which utilizes BCH for U-Boot section in SPL):
Hi Andreas,
Thanks for your response---this was very helpful. When I boot my board using the tricorder board file, it flashes nand correctly. Likewise, I moved over some of the NAND configuration from include/configs/tricorder.h to include/configs/omap3_overo.h and, after a little rearranging to enlarge SPL, it also flashed NAND correctly.
So...any guesses what it is about setting these variables that gets NAND flashing to work properly?
+#define CONFIG_NAND_OMAP_BCH8 +#define CONFIG_BCH -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}+#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20, \
21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\60, 61, 62, 63}-#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCBYTES 13
--Ash