If the fifo-size DT parameter is not provided then probe the controller's fifo depth at runtime. This is ported from a patch in the Linux Xilinx SPI driver.
Signed-off-by: Mayuresh Chitale mchitale@ventanamicro.com Reviewed-by: Michal Simek michal.simek@amd.com Link: https://lore.kernel.org/r/1422029330-10971-5-git-send-email-ricardo.ribalda@... --- drivers/spi/xilinx_spi.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index b63cda2091..94ddf4967e 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -109,6 +109,27 @@ struct xilinx_spi_priv { u8 startup; };
+static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs *regs) +{ + u8 sr; + int n_words = 0; + + /* + * Before the buffer_size detection reset the core + * to make sure to start with a clean state. + */ + writel(SPISSR_RESET_VALUE, ®s->srr); + + /* Fill the Tx FIFO with as many words as possible */ + do { + writel(0, ®s->spidtr); + sr = readl(®s->spisr); + n_words++; + } while (!(sr & SPISR_TX_FULL)); + + return n_words; +} + static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); @@ -116,6 +137,8 @@ static int xilinx_spi_probe(struct udevice *bus)
regs = priv->regs = dev_read_addr_ptr(bus); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); + if (!priv->fifo_depth) + priv->fifo_depth = xilinx_spi_find_buffer_size(regs);
writel(SPISSR_RESET_VALUE, ®s->srr);