Hello all,
After a lot of
reading of code, FAQs, and this list, I have successfully ported U-Boot to my
custom PowerPC 852T platform. (And by the way, all you out there that
have problems with SDRAM… make sure your UPM tables are right; cost me a
day for two mistyped values.) However, I ran into something that I call
unusual, and would like some advice/opinions.
My board boots to
address 0x0, with FLASH located there. The desired location for FLASH
memory will be at 0x0400_0000. This is the address space to which I link
U-Boot. The way I understand U-Boot to work is that for PPC8xx platforms,
FLASH memory is generally located at address 0x0, and CS0 is required to map
both address 0x0 and your absolute address space (0x0400_0000 in my example) so
it can seamlessly jump from one to the other. Later on, when SDRAM needs
to be initialized, all chip selects 0-7 are configured based on definitions in
your board’s config include file.
Assuming this is
correct, I found that my platform would not run past the jump from address
space mapped at 0x0 to address space mapped at 0x0400_0000, and I boiled it
down to values in CS0’s option register that are contrary to what I require.
What I ended up doing is program CS0 base and option registers with what I call
‘boot’ values, to correctly configure OR0 to allow this duplication
of address space for FLASH. This was done immediately prior to the
jumpoff point. Everything from that point on was per normal U-Boot
startup (including the remapping of CS0 later on). This puts my platform
into a known state that correctly maps all peripheral devices with their proper
sizing and address masks.
Is this something
uncommon or am I missing something obvious? Is this contrary to the goals
for U-Boot’s architecture at startup of PPC8xx processors? Or is
this possibly something one would like to see incorporated into U-Boot?
Any advice/comments are
appreciated…
TIA,
Steve
------
Network Solutions
Group
Hypercom Corporation