This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com Reviewed-by: Jagan Teki jagan@openedev.com Reviewed-by: Simon Glass sjg@chromium.org --- v9: no changes v8: no changes v7: no changes v6: no changes v5: no changes v4: no changes v3: rename BCM6338 SPI driver to BCM6348 v2: add spi alias
arch/mips/dts/brcm,bcm6338.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a4372b..0cab44cb8d 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338";
+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -109,6 +113,19 @@ status = "disabled"; };
+ spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6338_CLK_SPI>; + resets = <&periph_rst BCM6338_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe3100 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe3100 0x38>;