CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- board/freescale/mpc8308rdb/sdram.c | 4 ++-- board/freescale/mpc8313erdb/sdram.c | 8 ++++---- board/freescale/mpc8315erdb/sdram.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 8 ++++---- board/freescale/mpc8349itx/mpc8349itx.c | 8 ++++---- board/freescale/mpc837xemds/mpc837xemds.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +- board/gdsys/mpc8308/sdram.c | 4 ++-- board/ids/ids8313/ids8313.c | 2 +- board/mpc8308_p1m/sdram.c | 4 ++-- board/sbc8349/sbc8349.c | 8 ++++---- board/ve8313/ve8313.c | 8 ++++---- drivers/ddr/fsl/main.c | 4 ++++ include/configs/MPC8308RDB.h | 1 - include/configs/MPC8313ERDB_NAND.h | 1 - include/configs/MPC8313ERDB_NOR.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/TQM834x.h | 1 - include/configs/caddy2.h | 1 - include/configs/hrcon.h | 1 - include/configs/ids8313.h | 1 - include/configs/kmcoge5ne.h | 1 - include/configs/kmeter1.h | 1 - include/configs/kmopti2.h | 1 - include/configs/kmsupx5.h | 1 - include/configs/kmtegr1.h | 1 - include/configs/kmtepr2.h | 1 - include/configs/kmvect1.h | 1 - include/configs/mpc8308_p1m.h | 1 - include/configs/sbc8349.h | 1 - include/configs/strider.h | 1 - include/configs/suvd3.h | 1 - include/configs/tuge1.h | 1 - include/configs/tuxx1.h | 1 - include/configs/ve8313.h | 1 - include/configs/vme8349.h | 1 - 44 files changed, 35 insertions(+), 61 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index b3cbf9f8823..5ca307ca583 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -281,7 +281,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index e64b3107b5f..317e63ea6a1 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -33,7 +33,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -61,7 +61,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 5e074e3d87b..090412d4b6c 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -47,7 +47,7 @@ static long fixed_sdram(void) volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -57,12 +57,12 @@ static long fixed_sdram(void) */ __udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index b9f94c83324..2f0f29a0e57 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -44,7 +44,7 @@ static long fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 1c34f1dc38c..cfa2524df6d 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -91,7 +91,7 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(ddr_size);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256) @@ -112,12 +112,12 @@ int fixed_sdram(void) im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index aaaea7ce89f..81b3f00b56e 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -37,14 +37,14 @@ int fixed_sdram(void)
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 09a046dff8d..16922087c01 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -252,7 +252,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CONFIG_SYS_DDR_SIZE != 512) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index d9a47b90b2f..18f396aac8b 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -95,7 +95,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 5ced8eb0819..3eb0e37b7b5 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,7 +34,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -62,7 +62,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index f2ccabc3162..ff3265c1dc6 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); sync(); diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c index 4118c019ccf..baf70d8807b 100644 --- a/board/mpc8308_p1m/sdram.c +++ b/board/mpc8308_p1m/sdram.c @@ -29,7 +29,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -57,7 +57,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 5584b3d1796..e51eeae065d 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -79,19 +79,19 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 609585bc653..f4148a21e3b 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -38,7 +38,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -48,12 +48,12 @@ static long fixed_sdram(void) */ __udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif out_be32(&im->ddr.csbnds[0].csbnds, - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA)); out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 6d018fde2b2..e1f69a1d25c 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -23,8 +23,12 @@ * 0x80_8000_0000 ~ 0xff_ffff_ffff */ #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#else #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif +#endif
#ifdef CONFIG_PPC #include <asm/fsl_law.h> diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d9361fd8a03..5d31d4a0b6b 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,7 +37,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c83996c73..6f100fc7e7b 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -87,7 +87,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 083eac0ce3f..582c7329cee 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c5a229deb4c..0b94b0c5cf9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 3e6febfc9d3..a90a9a86f8d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -24,7 +24,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
#undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4b3f70c916c..88b6f873978 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -21,7 +21,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1a96be0895c..fdbd15ea93e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 311f87b5b3c..1e0e297351e 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index bb3bcfcc448..388910ac38d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -143,7 +143,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e34a36cadd8..61f9eaf7150 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -36,7 +36,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 33d4ced92f7..07b206ff9f9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 53fac4d675a..0da34d05afc 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -25,7 +25,6 @@ */ /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f14e5faafa6..928136f325f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index ae3fcfd3d79..d73e848b0c7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 1d56d24c15a..8bcd305c490 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -52,7 +52,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index fc60b01d38c..de6925581a9 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -46,7 +46,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 644cc0ff098..e900439cbab 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index bcdce27566f..aa0f7f1de1c 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 94cbcf58fe5..9f97a5f3ee2 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index c8e5d303b10..9b89f7b985e 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 2673ecbb905..b80f36c69ee 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 4ad30453f68..8ff7571866e 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8836b70b762..0392c3e8b40 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -40,7 +40,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 709387ecf79..b4ae7b75543 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -47,7 +47,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index c01531c3ca2..e92bd1e8f10 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 72ed00fce75..e8fe19ca4e7 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 005d114510d..f6d067b97b8 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 62e9db4e1b8..8fa2913850b 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index cd6c686b890..2116d6bbcf8 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 14a84fabc97..1bce6c732d9 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING