Hi Jerry,
It looks to me like for the M%282 board the PHY address is determined by querying the MII interface:
include/configs/M5282EVB.h
#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 # define CFG_DISCOVER_PHY ...
This cause the code in ./drivers/net/mcffec.c specifically mii_discover_phy to be run, I tried to enable the debugging in this code:
//#undef ET_DEBUG //#undef MII_DEBUG
but it does not seem to print anything (:(). One interesting feature is that once my uClinux image has booted I can talk to it over the switched network just fin. So the issue is really something in the setup of the MII PHY interface in u-boot. Is there any build target to allow me to try and debug this?
Thanks.
Alex
On Mon, 19 Jan 2009 20:14:07 -0500 Jerry Van Baren gvb.uboot@gmail.com wrote:
Hi Loren,
Please don't top post. It annoys us curmudgeons.
Loren A. Linden Levy wrote:
Hi All,
I still have not found a solution and I am a bit desperate. I did not seem to be able to send any packets (using ping) from the FECO on the M5282Lite board to the tftp host, however pings from the host were answered and I saw packets going from the coldfire board to the host in wireshark. I also get a strange error when I ask for mii info:
uBOOT=>> mii device MII devices: 'FEC0' Current device: 'FEC0
uBOOT=>> mii info MII not complete MII not complete ...
a dump gives me:
uBOOT=>> mii dump MII not complete 0. (ffff) -- PHY control register -- (8000:8000) 0.15 = 1 reset (4000:4000) 0.14 = 1 loopback (2040:2040) 0. 6,13 = b11 speed selection = ??? Mbps (1000:1000) 0.12 = 1 A/N enable (0800:0800) 0.11 = 1 power-down (0400:0400) 0.10 = 1 isolate (0200:0200) 0. 9 = 1 restart A/N (0100:0100) 0. 8 = 1 duplex = full (0080:0080) 0. 7 = 1 collision test enable (003f:003f) 0. 5- 0 = 63 (reserved)
Note that ALL the bits are '1'. That is indicating your PHY is NOT DRIVING data on the MII data line (always idle high). Odds are really good that you are not driving your MII clock and data properly, your PHY isn't at the address you think it is at, or your hardware has problems. The only reason you are getting any ether activity is likely because your PHY is defaulting to a configuration that is mostly (not entirely) broken.
- Double-check your MII clock and data pin configurations. Are you
initializing them correctly? Error probability: 87%.
- What address is your PHY strapped to? You need to know this. Error
probability: 11% (your emails imply you don't know this - I bumped the probability up because of that impression).
- Use a logic analyzer (preferred), o-scope (good) or a logic probe on
your PHY's MII clock and data lines and verify they are receiving the right sequence (or at least wiggling when you do the MII commands). With a logic analyzer you should be able to read the data you are sending and verify the bit pattern. You can do this with an o-scope (especially a digital one) too, but a little trickier. This is likely a software error (above 87% + 11%) - hardware error probability: 2%
- Oh yeah, you might be clocking the MII lines too fast. Pretty small
probability, though.
[snip]
Good luck and happy probing, gvb
P.S. I used mostly odd percentages because I read somewhere that made up percentages are more believable when they are odd. ;-)