Thanks Stefan for your comments. Please see reply below.
mtdcr(plb1_acr, plb1_acr_ppm_fair |plb1_acr_hbu_enabled |plb1_acr_rdp_4deep |plb1_acr_wrp_2deep);Is this PLB0_ACR tuning Canyonlands specific? Or will all 460EX/GT boards profit from this configuration? Or even other 4xx PPC variants as well?
If this is the case then I suggest to move this code to a common place, perhaps in cpu_init_f(). What do you think?
The PLB Arbiter register configuration are definitely common to PPC460EX/GT boards. I am working with PowerPC hardware architects to find out whether we can put the same changes for other PPC4xx variants
mtdcr(SDRAM_CONF1HB, 0x80001c80);mtdcr(SDRAM_CONF1LL, 0x80001c80);mtdcr(SDRAM_CONFPATHB, 0x18a68000);Could you please add a comment what exactly is configured with these "magic numbers"?
I will add C defines corresponding to those register bits and resubmit
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
Are the PLBx_ACR register really identical on all those PPC's? Just checking.
They seem to be so. I will double-check the user manuals for all these processors.
Please fix if necessary and resubmit. And please keep me on CC on 4xx related patches.
I will try to put out the modified patch latest by tommorow.
Best Regards, Prodyut Hazarika
================================ Staff S/W Engineer AMCC ================================