On 06/04/2012 15:25, Marek Vasut wrote:
We certainly don't want the compiler to reorganise the code for dcache flushing.
Signed-off-by: Marek Vasut marex@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net
arch/arm/cpu/arm926ejs/cache.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 5b23e3a..0b36294 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -82,7 +82,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) start += CONFIG_SYS_CACHELINE_SIZE; }
- asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
- asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
}
void flush_cache(unsigned long start, unsigned long size)
Acked-by: Stefano Babic sbabic@denx.de
Thanks to point this issue - the same happens on MX3x. I will send a patch (ptch for cache in ARM1136 is already merged).
Stefano