Hello York,
Please see response inline
Regards Ashish
-----Original Message----- From: York Sun [mailto:york.sun@nxp.com] Sent: Wednesday, April 12, 2017 2:04 AM To: Ashish Kumar ashish.kumar@nxp.com; u-boot@lists.denx.de; u-boot@linux.freescale.net Cc: Alison Wang alison.wang@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Raghav Dogra raghav.dogra@nxp.com; Shaohui Xie Shaohui.Xie@nxp.com Subject: Re: [Patch v2 1/3] armv8: ls1088a: Add NXP LS1088A SoC support
On 04/10/2017 09:19 AM, Ashish Kumar wrote:
The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications.
LS1088A is compliant to the Layerscape Chassis Generation 3.
Features summary:
- Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- Cache coherent interconnect (CCI-400)
- One 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Alison Wang alison.wang@nxp.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com Signed-off-by: Raghav Dogra raghav.dogra@nxp.com Signed-off-by: Shaohui Xie Shaohui.Xie@nxp.com
Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com
v2: Fix indentaion in commit msg Separate RDB and Si specific file Move Macros to Kconfig
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 44 ++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 10 ++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 6 +- arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 + arch/arm/dts/fsl-ls1088a.dtsi | 78 +++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 62 +++++++++- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 + .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 3 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 11 ++ .../asm/arch-fsl-layerscape/ls1088a_stream_id.h | 57 ++++++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 + drivers/ddr/fsl/util.c | 2 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/net/ldpaa_eth/ls1088a.c | 87 ++++++++++++++ 17 files changed, 494 insertions(+), 11 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls1088a_stream_id.h create mode 100644 drivers/net/ldpaa_eth/ls1088a.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index fbb95cd..a3e8499 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -49,6 +49,29 @@ config ARCH_LS1046A select BOARD_EARLY_INIT_F select SYS_FSL_HAS_CCI400
+config ARCH_LS1088A
- bool
- select ARMV8_SET_SMPEN
- select FSL_LSCH3
- select SYS_FSL_DDR
- select SYS_FSL_DDR_LE
- select SYS_FSL_DDR_VER_50
- select SYS_FSL_HAS_CCI400
- select SYS_FSL_HAS_DDR4
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_COMPAT_5
- select SYS_FSL_SEC_LE
- select SYS_FSL_SRDS_1
- select SYS_FSL_SRDS_2
- select FSL_TZASC_1
- select SYS_FSL_ERRATUM_A009803
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_A010165
- select SYS_FSL_ERRATUM_A008511
- select SYS_FSL_ERRATUM_A008850
- select ARCH_EARLY_INIT_R
- select BOARD_EARLY_INIT_F
config ARCH_LS2080A bool select ARMV8_SET_SMPEN @@ -79,6 +102,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009203
- select SYS_FSL_HAS_CCN504 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
@@ -97,7 +121,7 @@ config FSL_LSCH3
config FSL_MC_ENET bool "Management Complex network"
- depends on ARCH_LS2080A
- depends on ARCH_LS2080A || ARCH_LS1088A default y select RESV_RAM help
@@ -113,6 +137,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A
- default "fsl,ls1080a-pcie" if ARCH_LS1088A help This compatible is used to find pci controller node in Kernel DT to complete fixup.
@@ -173,6 +198,7 @@ config MAX_CPUS default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A
- default 8 if ARCH_LS1088A default 1 help Set this number to the maximum number of possible CPUs in the SoC.
@@ -195,13 +221,11 @@ config QSPI_AHB_INIT
config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A ||
+ARCH_LS1088A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A
- default 8 if ARCH_LS2080A
- default 8 if ARCH_LS2080A || ARCH_LS1088A
-config SYS_FSL_HAS_CCI400
- bool
config SYS_FSL_HAS_DP_DDR bool @@ -244,6 +268,7 @@ config SYS_FSL_PCLK_DIV int "Platform clock divider" default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A
- default 1 if ARCH_LS1088A default 2 help This is the divider that is used to derive Platform clock from @@
-313,6 +338,12 @@ config RESV_RAM config SYS_FSL_ERRATUM_A009203 bool
+config SYS_FSL_HAS_CCI400
- bool
+config SYS_FSL_HAS_CCN504
- bool
Unless you are doing cleanup, don't move them. [Ashish Kumar] Will take care in next version
config SYS_FSL_ERRATUM_A008336 bool
@@ -337,7 +368,8 @@ config SYS_FSL_ERRATUM_A009929 config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM
- default 0x20000000
- default 0x20000000 if ARCH_LS2080A
- default 0x70000000 if ARCH_LS1088A help Reserved memory needs to be aligned for MC to use. Default value is 512MB.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index c9ab93e..cfad154 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -38,3 +38,7 @@ endif ifneq ($(CONFIG_ARCH_LS1046A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o endif
+ifneq ($(CONFIG_ARCH_LS1088A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index a826e33..a56cad5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -14,6 +14,7 @@ #include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/speed.h> +#include <fsl_immap.h> #ifdef CONFIG_MP #include <asm/arch/mp.h> #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 955e0b7..d7e2d3c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) return; }
+__weak int serdes_get_number(int serdes, int cfg) {
- return cfg;
+}
How about this
/* If serdes is not enabled, return an error. */ __weak int serdes_get_number(int serdes, int cfg) { return cfg > 0 : cfg ? -ENODEV; } [Ashish Kumar] It is taken care here in function
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { . . . /* Is serdes enabled at all? */ if (cfg == 0) return -ENODEV;
York