Remove SECURE_IOU option which is not needed. U-Boot itself can detect which EL level it is on and based on that use do platform setup. It also simplify usage because one Kconfig entry is gone.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/cpu/armv8/zynqmp/Kconfig | 4 ---- arch/arm/cpu/armv8/zynqmp/clk.c | 16 ++++++++++++++++ arch/arm/cpu/armv8/zynqmp/cpu.c | 14 ++++++++++++++ arch/arm/include/asm/arch-zynqmp/clk.h | 1 + arch/arm/include/asm/arch-zynqmp/hardware.h | 24 ++++++++++++++++++++---- board/xilinx/zynqmp/zynqmp.c | 17 +++++++++++++---- 6 files changed, 64 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e5a4fdd0fda0..9a19dfa77f79 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -20,10 +20,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
-config SECURE_IOU - bool "Configure ZynqMP secure IOU" - default n - config ZYNQMP_USB bool "Configure ZynqMP USB"
diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 9218586e94a3..40bd2ca213a8 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -26,6 +26,22 @@ unsigned long get_uart_clk(int dev_id) return 133000000; }
+unsigned long zynqmp_get_system_timer_freq(void) +{ + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 10000; + case ZYNQMP_CSU_VERSION_EP108: + return 4000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } + + return 100000000; +} + #ifdef CONFIG_CLOCKS /** * set_cpu_clk_info() - Initialize clock framework diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f90cca36aa72..45b49dc0182e 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -15,8 +15,22 @@
DECLARE_GLOBAL_DATA_PTR;
+static unsigned int zynqmp_get_silicon_version_secure(void) +{ + u32 ver; + + ver = readl(&csu_base->version); + ver &= ZYNQMP_SILICON_VER_MASK; + ver >>= ZYNQMP_SILICON_VER_SHIFT; + + return ver; +} + unsigned int zynqmp_get_silicon_version(void) { + if (current_el() == 3) + return zynqmp_get_silicon_version_secure(); + gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) { diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h index d55bc31c4399..b18333d1ca25 100644 --- a/arch/arm/include/asm/arch-zynqmp/clk.h +++ b/arch/arm/include/asm/arch-zynqmp/clk.h @@ -9,5 +9,6 @@ #define _ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_id); +unsigned long zynqmp_get_system_timer_freq(void);
#endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index bbf89d9dd746..5f4cfe3b6b68 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -41,11 +41,8 @@ struct crlapb_regs {
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
-#if defined(CONFIG_SECURE_IOU) -#define ZYNQMP_IOU_SCNTR 0xFF260000 -#else +#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 #define ZYNQMP_IOU_SCNTR 0xFF250000 -#endif #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
@@ -57,6 +54,14 @@ struct iou_scntr {
#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
+struct iou_scntr_secure { + u32 counter_control_register; + u32 reserved0[7]; + u32 base_frequency_id_register; +}; + +#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) + /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F #define SD_MODE 0x00000003 @@ -106,9 +111,20 @@ struct apu_regs { #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
/* Board version value */ +#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3
+#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 + +struct csu_regs { + u32 reserved0[17]; + u32 version; +}; + +#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 2cf47125d433..63c332f03dc2 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,6 +9,7 @@ #include <netdev.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -28,10 +29,18 @@ int board_early_init_r(void) { u32 val;
- val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - + if (current_el() == 3) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); + } /* Program freq register in System counter and enable system counter */ writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |