Hi Marcel,
Il giorno 24 ott 2022, alle ore 00:13, Marcel Ziswiler marcel.ziswiler@toradex.com ha scritto:
Hi Giulio
On Sun, 2022-10-23 at 01:47 +0200, Giulio Benetti wrote: Hi Marcel,
Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++++++++++-- arch/arm/dts/imxrt1050-evk.dts | 257 +++----------------- arch/arm/dts/imxrt1050-pinfunc.h | 2 +- arch/arm/dts/imxrt1050.dtsi | 168 ++++++------- include/dt-bindings/clock/imxrt1050-clock.h | 9 +- 5 files changed, 255 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi index 617cece448..bf40ada234 100644 --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi @@ -4,8 +4,12 @@
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
*/
+#include <dt-bindings/memory/imxrt-sdram.h> +#include "imxrt1050-pinfunc.h"
- / { chosen {
tick-timer = &gpt; u-boot,dm-spl; };@@ -15,6 +19,52 @@
soc { u-boot,dm-spl;
semc@402f0000 {compatible = "fsl,imxrt-semc";clocks = <&clks IMXRT1050_CLK_SEMC>;pinctrl-0 = <&pinctrl_semc>;pinctrl-names = "default";reg = <0x402f0000 0x4000>;status = "okay";u-boot,dm-spl;/** Memory configuration from sdram datasheet IS42S16160J-6BLI*/fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8MUX_CSX0_SDRAM_CS10000>;fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITSBL_8COL_9BITSCL_3>;fsl,sdram-timing = /bits/ 8 <0x20x20x90x10x50x60x200x090x010x000x040x0A0x210x50>;bank1: bank@0 {fsl,base-address = <0x80000000>;fsl,memory-size = <MEM_SIZE_32M>;u-boot,dm-spl;};}; };@@ -50,41 +100,121 @@ u-boot,dm-spl; };
-&gpt1 { +&gpt {
clocks = <&osc>;compatible = "fsl,imxrt-gpt";status = "okay"; u-boot,dm-spl;};
&lpuart1 { /* console */
compatible = "fsl,imxrt-lpuart"; u-boot,dm-spl;};
-&semc {
u-boot,dm-spl;bank1: bank@0 {u-boot,dm-spl;};-};
&iomuxc { u-boot,dm-spl;
imxrt1050-evk { u-boot,dm-spl;pinctrl_lpuart1: lpuart1grp {u-boot,dm-spl;}; pinctrl_semc: semcgrp {u-boot,dm-spl;};pinctrl_usdhc0: usdhc0grp {
fsl,pins = <MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA000xf1 /* SEMC_D0 */MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA010xf1 /* SEMC_D1 */MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA020xf1 /* SEMC_D2 */MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA030xf1 /* SEMC_D3 */MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA040xf1 /* SEMC_D4 */MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA050xf1 /* SEMC_D5 */MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA060xf1 /* SEMC_D6 */MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA070xf1 /* SEMC_D7 */MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM000xf1 /* SEMC_DM0 */MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR000xf1 /* SEMC_A0 */MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR010xf1 /* SEMC_A1 */MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR020xf1 /* SEMC_A2 */MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR030xf1 /* SEMC_A3 */MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR040xf1 /* SEMC_A4 */MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR050xf1 /* SEMC_A5 */MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR060xf1 /* SEMC_A6 */MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR070xf1 /* SEMC_A7 */MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR080xf1 /* SEMC_A8 */MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR090xf1 /* SEMC_A9 */MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR110xf1 /* SEMC_A11 */MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR120xf1 /* SEMC_A12 */MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA00xf1 /* SEMC_BA0 */MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA10xf1 /* SEMC_BA1 */MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR100xf1 /* SEMC_A10 */MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS0xf1 /* SEMC_CAS */MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS0xf1 /* SEMC_RAS */MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK0xf1 /* SEMC_CLK */MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE0xf1 /* SEMC_CKE */MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE0xf1 /* SEMC_WE */MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS00xf1 /* SEMC_CS0 */MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA080xf1 /* SEMC_D8 */MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA090xf1 /* SEMC_D9 */MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA100xf1 /* SEMC_D10 */MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA110xf1 /* SEMC_D11 */MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA120xf1 /* SEMC_D12 */MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA130xf1 /* SEMC_D13 */MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA140xf1 /* SEMC_D14 */MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA150xf1 /* SEMC_D15 */MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM010xf1 /* SEMC_DM1 */MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS(IMX_PAD_SION | 0xf1) /* SEMC_DQS */>; u-boot,dm-spl; }; };+&pinctrl_lpuart1 {
u-boot,dm-spl;+};
+&pinctrl_usdhc0 {
u-boot,dm-spl;+};
- &usdhc1 {
compatible = "fsl,imxrt-usdhc"; u-boot,dm-spl;diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index fb2da3adfc..6a9c10decf 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
@@ -6,7 +6,6 @@
/dts-v1/; #include "imxrt1050.dtsi" -#include "imxrt1050-evk-u-boot.dtsi"
Why do you drop this ^^^ include?
As this one gets automatically included by the U-Boot build system and them regular device trees should just come from the Linux kernel with any and all U-Boot specific changes being done in such aforementioned -u- boot.dtsi device tree include files.
So please as for patch for 1020 add a note of this in commit log.
#include "imxrt1050-pinfunc.h"
/ { @@ -14,210 +13,52 @@ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
chosen {
bootargs = "root=/dev/ram";stdout-path = "serial0:115200n8";tick-timer = &gpt1;
stdout-path = &lpuart1; };
memory {
aliases {gpio0 = &gpio1;gpio1 = &gpio2;gpio2 = &gpio3;gpio3 = &gpio4;gpio4 = &gpio5;mmc0 = &usdhc1;serial0 = &lpuart1;};memory@80000000 { device_type = "memory"; reg = <0x80000000 0x2000000>; };-&lpuart1 { /* console */ +&lpuart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart1>; status = "okay"; };
-&semc {
/** Memory configuration from sdram datasheet IS42S16160J-6BLI*/fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8MUX_CSX0_SDRAM_CS10000>;fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITSBL_8COL_9BITSCL_3>;fsl,sdram-timing = /bits/ 8 <0x20x20x90x10x50x60x200x090x010x000x040x0A0x210x50>;bank1: bank@0 {fsl,base-address = <0x80000000>;fsl,memory-size = <MEM_SIZE_32M>;};-};
- &iomuxc { pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;imxrt1050-evk {pinctrl_lpuart1: lpuart1grp {fsl,pins = <MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD0xf1MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD0xf1>;};pinctrl_semc: semcgrp {fsl,pins = <MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA000xf1 /* SEMC_D0 */MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA010xf1 /* SEMC_D1 */MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA020xf1 /* SEMC_D2 */MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA030xf1 /* SEMC_D3 */MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA040xf1 /* SEMC_D4 */MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA050xf1 /* SEMC_D5 */MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA060xf1 /* SEMC_D6 */MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA070xf1 /* SEMC_D7 */MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM000xf1 /* SEMC_DM0 */MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR000xf1 /* SEMC_A0 */MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR010xf1 /* SEMC_A1 */MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR020xf1 /* SEMC_A2 */MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR030xf1 /* SEMC_A3 */MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR040xf1 /* SEMC_A4 */MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR050xf1 /* SEMC_A5 */MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR060xf1 /* SEMC_A6 */MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR070xf1 /* SEMC_A7 */MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR080xf1 /* SEMC_A8 */MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR090xf1 /* SEMC_A9 */MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR110xf1 /* SEMC_A11 */MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR120xf1 /* SEMC_A12 */MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA00xf1 /* SEMC_BA0 */MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA10xf1 /* SEMC_BA1 */MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR100xf1 /* SEMC_A10 */MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS0xf1 /* SEMC_CAS */MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS0xf1 /* SEMC_RAS */MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK0xf1 /* SEMC_CLK */MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE0xf1 /* SEMC_CKE */MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE0xf1 /* SEMC_WE */MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS00xf1 /* SEMC_CS0 */MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA080xf1 /* SEMC_D8 */MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA090xf1 /* SEMC_D9 */MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA100xf1 /* SEMC_D10 */MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA110xf1 /* SEMC_D11 */MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA120xf1 /* SEMC_D12 */MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA130xf1 /* SEMC_D13 */MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA140xf1 /* SEMC_D14 */MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA150xf1 /* SEMC_D15 */MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM010xf1 /* SEMC_DM1 */MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS(IMX_PAD_SION | 0xf1) /* SEMC_DQS */>;};pinctrl_usdhc0: usdhc0grp {fsl,pins = <MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B0x1B000MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT0xB069MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD0x17061MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK0x17061MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA30x17061MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA20x17061MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA10x17061MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA00x17061>;};pinctrl_lcdif: lcdifgrp {fsl,pins = <MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069>;};
pinctrl_lpuart1: lpuart1grp {fsl,pins = <MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1>; };-};
-&gpt1 {
status = "okay";
pinctrl_usdhc0: usdhc0grp {fsl,pins = <MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061>;};};
&usdhc1 {
@@ -226,42 +67,6 @@ pinctrl-1 = <&pinctrl_usdhc0>; pinctrl-2 = <&pinctrl_usdhc0>; pinctrl-3 = <&pinctrl_usdhc0>;
status = "okay";cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;-};
-&lcdif {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_lcdif>;display = <&display0>;status = "okay";display0: display0 {bits-per-pixel = <16>;bus-width = <16>;display-timings {timing0: timing0 {clock-frequency = <9300000>;hactive = <480>;vactive = <272>;hback-porch = <4>;hfront-porch = <8>;vback-porch = <4>;vfront-porch = <8>;hsync-len = <41>;vsync-len = <10>;de-active = <1>;pixelclk-active = <0>;hsync-active = <0>;vsync-active = <0>;};};};-};
-&usbotg1 {
dr_mode = "host"; status = "okay";diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h index a29031ab3d..22c14a3262 100644 --- a/arch/arm/dts/imxrt1050-pinfunc.h +++ b/arch/arm/dts/imxrt1050-pinfunc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index 09f4712af6..03e6a858a7 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
@@ -8,53 +8,37 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/imxrt1050-clock.h> #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/memory/imxrt-sdram.h>
/ { #address-cells = <1>; #size-cells = <1>;
aliases {display0 = &lcdif;gpio0 = &gpio1;gpio1 = &gpio2;gpio2 = &gpio3;gpio3 = &gpio4;gpio4 = &gpio5;mmc0 = &usdhc1;serial0 = &lpuart1;usbphy0 = &usbphy1;};clocks { osc: osc {compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; };
};soc {semc: semc@402f0000 {compatible = "fsl,imxrt-semc";reg = <0x402f0000 0x4000>;clocks = <&clks IMXRT1050_CLK_SEMC>;pinctrl-0 = <&pinctrl_semc>;pinctrl-names = "default";status = "okay";
osc3M: osc3M {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <3000000>; };};soc { lpuart1: serial@40184000 {
compatible = "fsl,imxrt-lpuart";
compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x40184000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <20>; clocks = <&clks IMXRT1050_CLK_LPUART1>;
clock-names = "per";
clock-names = "ipg"; status = "disabled"; };
iomuxc: iomuxc@401f8000 {compatible = "fsl,imxrt-iomuxc";
iomuxc: pinctrl@401f8000 {compatible = "fsl,imxrt1050-iomuxc"; reg = <0x401f8000 0x4000>; fsl,mux_mask = <0x7>; };@@ -64,31 +48,61 @@ reg = <0x400d8000 0x4000>; };
clks: ccm@400fc000 {
clks: clock-controller@400fc000 { compatible = "fsl,imxrt1050-ccm"; reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <95>, <96>;clocks = <&osc>;clock-names = "osc"; #clock-cells = <1>;
};usdhc1: usdhc@402c0000 {compatible = "fsl,imxrt-usdhc";reg = <0x402c0000 0x10000>;interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clks IMXRT1050_CLK_USDHC1>;clock-names = "per";
assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,<&clks IMXRT1050_CLK_PLL1_BYPASS>,<&clks IMXRT1050_CLK_PLL2_BYPASS>,<&clks IMXRT1050_CLK_PLL3_BYPASS>,<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,<&clks IMXRT1050_CLK_PLL1_ARM>,<&clks IMXRT1050_CLK_PLL2_SYS>,<&clks IMXRT1050_CLK_PLL3_USB_OTG>,<&clks IMXRT1050_CLK_PLL3_USB_OTG>,<&clks IMXRT1050_CLK_PLL2_SYS>;};edma1: dma-controller@400e8000 {#dma-cells = <2>;compatible = "fsl,imx7ulp-edma";reg = <0x400e8000 0x4000>,<0x400ec000 0x4000>;dma-channels = <32>;interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;clock-names = "dma", "dmamux0";clocks = <&clks IMXRT1050_CLK_DMA>,<&clks IMXRT1050_CLK_DMA_MUX>;};usdhc1: mmc@402c0000 {compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";reg = <0x402c0000 0x4000>;interrupts = <110>;clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,<&clks IMXRT1050_CLK_OSC>,<&clks IMXRT1050_CLK_USDHC1>;clock-names = "ipg", "ahb", "per"; bus-width = <4>;fsl,wp-controller;no-1-8-v;max-frequency = <4000000>; fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>; status = "disabled"; }; gpio1: gpio@401b8000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <80>, <81>; gpio-controller; #gpio-cells = <2>; interrupt-controller;@@ -96,10 +110,9 @@ };
gpio2: gpio@401bc000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <82>, <83>; gpio-controller; #gpio-cells = <2>; interrupt-controller;@@ -107,10 +120,9 @@ };
gpio3: gpio@401c0000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <84>, <85>; gpio-controller; #gpio-cells = <2>; interrupt-controller;@@ -118,10 +130,9 @@ };
gpio4: gpio@401c4000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401c4000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <86>, <87>; gpio-controller; #gpio-cells = <2>; interrupt-controller;@@ -129,60 +140,21 @@ };
gpio5: gpio@400c0000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x400c0000 0x4000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <88>, <89>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; };
lcdif: lcdif@402b8000 {compatible = "fsl,imxrt-lcdif";reg = <0x402b8000 0x4000>;interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,<&clks IMXRT1050_CLK_LCDIF_APB>;clock-names = "pix", "axi";assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;status = "disabled";};please replace all lcdif related stuff since u-boot does support it while Linux still not. To have consistency we should add this node to Linux dts files too even if it's not supported. In the end .dts file is a description of the hardware.
Yes, I guess somebody should.
However, for now, I guess those should just go into the U-Boot specific include file as well.
gpt1: gpt1@401ec000 {compatible = "fsl,imxrt-gpt";
gpt: timer@401ec000 {compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; reg = <0x401ec000 0x4000>; interrupts = <100>;
clocks = <&osc>;status = "disabled";};usbphy1: usbphy@400d9000 {compatible = "fsl,imxrt-usbphy";reg = <0x400d9000 0x1000>;interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;};usbmisc: usbmisc@402e0800 {#index-cells = <1>;compatible = "fsl,imxrt-usbmisc";reg = <0x402e0800 0x200>;clocks = <&clks IMXRT1050_CLK_USBOH3>;};usbotg1: usb@402e0000 {compatible = "fsl,imxrt-usb", "fsl,imx27-usb";reg = <0x402e0000 0x200>;interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clks IMXRT1050_CLK_USBOH3>;fsl,usbphy = <&usbphy1>;fsl,usbmisc = <&usbmisc 0>;ahb-burst-config = <0x0>;tx-burst-size-dword = <0x10>;rx-burst-size-dword = <0x10>;status = "disabled";Same as lcdif, usbotg, ubsmisc and usbphy both supported in u-boot but still not in Linux. So they must be kept and Linux dts must be updated.
Okay, I will add them to the U-Boot specific include file for now. Will send a v4 with that shortly.
clocks = <&osc3M>;clock-names = "per"; }; };diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h index f74dbbcf93..93bef0832d 100644 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /*
- Copyright(C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
@@ -62,6 +62,11 @@ #define IMXRT1050_CLK_PLL7_USB_HOST 53 #define IMXRT1050_CLK_LCDIF_PIX 54 #define IMXRT1050_CLK_USBOH3 55 -#define IMXRT1050_CLK_END 56 +#define IMXRT1050_CLK_IPG_PDOF 56 +#define IMXRT1050_CLK_PER_CLK_SEL 57 +#define IMXRT1050_CLK_PER_PDOF 58 +#define IMXRT1050_CLK_DMA 59 +#define IMXRT1050_CLK_DMA_MUX 60 +#define IMXRT1050_CLK_END 61
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
I've given a fast review only on this patch since it's complex. I'll give another check soon.
Sure, much appreciated.
Have you tested this change too with the board?
No, but supposedly Jesse did. However, it was not fully clear to me whether such further changes may be required. Anyway, I hope one of you guys may test the v4 I am about to send out.
Yes, I will.
Waiting for V4 then.
Thank you!
Giulio
Thanks!
Thank you!
Best regards
Giulio Benetti CEO/CTO@Benetti Engineering sas
Cheers
Marcel